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參數(shù)資料
| 型號： | CLC020 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SMPTE 259M Digital Video Serializer with Integrated Cable Driver(SMPTE 259M數(shù)字視頻串行器帶集成電纜驅(qū)動器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 316K |
| 代理商： | CLC020 |
Device Operation
(Continued)
VIDEO DATA PROCESSING CIRCUITS
The
input data register
accepts 8 or 10-bit parallel data and
clock signals having CMOS/TTL-compatible signal levels.
Parallel data may conform to any of several standards:
SMPTE 125M, SMPTE 267M, SMPTE 244M or ITU-R
BT.601. If data is 8-bit, it is converted to a 10-bit representa-
tion according to the type of data being input: component
4:2:2 per SMPTE 259M paragraph 7.1.1, composite NTSC
per paragraph 8.1.1 or composite PAL per paragraph 9.1.1.
Output from this register feeds the SMPTE polynomial
generator/serializer and sync detector. All CMOS inputs in-
cluding the P
CLK
input have internal pull-down devices.
The
sync detector
or TRS character detector accepts data
from the input register. The detection function is controlled
by Sync Detect Enable, a low-true, TTL-compatible, external
signal. Synchronization words, the timing reference signals
(TRS), start-of-active-video (SAV) and end-of-active-video
(EAV) are defined in SMPTE 125M-1995 and 244M. The
sync detector supplies control signals to the SMPTE polyno-
mial generator that identify the presence of valid video data.
The
sync
detector
performs
LSB-clipping as prescribed in ITU-R-BT.601. LSB-clipping
causes all TRS characters with a value between 000h and
003h to be forced to 000h and all TRS characters with a
value between 3FCh and 3FFh to be forced to 3FFh. Clip-
ping is done prior to encoding.
The
SMPTE polynomial generator
accepts the parallel
video data and encodes it using the polynomial X
9
+X
4
+1 as
specified in SMPTE 259M–1997, paragraph 5 and Annex C.
The scrambled data is then serialized for output.
The
NRZ-to-NRZI converter
accepts serial NRZ data from
the SMPTE polynomial genertor and converts it to NRZI us-
ing the polynomial X + 1 per SMPTE 259M–1997, paragraph
5.2 and Annex C. The transmission bit order is LSB first, per
paragraph 6. The converter’s output feeds the output driver
amplifier.
input
TRS
character
PHASE-LOCKED LOOP AND VCO
The
phase-locked loop
(PLL) system generates the output
serial data clock at 10x the parallel data clock frequency.
This
system
consists
of
phase-frequency detector and internal loop filter. The VCO
free-running frequency is internally set. The PLL automati-
cally generates the appropriate frequency for the serial clock
rate using the parallel data clock (P
CLK
) frequency as its ref-
erence. Loop filtering is internal to the CLC020. The VCO
has separate V
SSO
and V
DDO
power supply feeds, pins 15
and 16, which may be supplied power independently via an
external low-pass filter, if desired. The PLL acquisition (lock)
time is less than 75 μs
@
270 Mbps.
a
VCO,
divider
chain,
LOCK DETECT
The
Lock Detect
output of the phase-frequency detector in-
dicates the PLL lock condition. It is a logic HIGH when the
loop is locked. The output is CMOS/TTL-compatible and is
suitable for driving other CMOS devices or a LED indicator.
SERIAL DATA OUTPUT BUFFER
The current-mode
serial data outputs
provide low-skew
complimentary or differential signals. The output buffer de-
sign can drive 75
coaxial cables (AC-coupled) or 10k/100k
ECL/PECL-compatible devices (DC-coupled). Output levels
are 800 mV
±
10% into 75
AC-coupled, back-matched
loads. The output level is 400 mV
P-P
±
10% when
DC-coupled into 75
(See Application Information for de-
tails). The 75
resistors connected to the SDO outputs are
back-matching resistors. No series back-matching resistors
should be used. SDO output levels are controlled by the
value of R
REF
connected to pin 19. The value of R
REF
is nor-
mally 1.69 k
,
±
1%. The output buffer is static when the de-
vice is in an out-of-lock condition. Separate V
SSSD
and
V
power feeds, pins 21 and 24, are provided for the se-
rial output driver.
POWER-ON RESET
The CLC020 has an internally controlled, automatic,
power-on reset
circuit. This circuit clears TRS detection cir-
cuitry, all latches, registers, counters and polynomial genera-
tors and disables the serial output. The SDO outputs are
tri-stated during power-on reset. The part will remain in the
reset condition until the parallel input clock is applied.
BUILT-IN SELF-TEST (BIST)
The CLC020 has a
built-in self-test (BIST)
function. The
BIST performs a comprehensive go-no-go test of the device.
The test uses either a full-field color bar for NTSC or a PLL
pathological for PAL as the test data pattern. Data is input in-
ternally to the input data register, processed through the de-
vice and tested for errors. Table 1 gives device pin functions
and Table 2 gives the test pattern codes used for this func-
tion. The signal level at Test_Output, pin 26, indicates a pass
or fail condition.
The BIST is initiated by applying the code for the desired
BIST to D0 throught D3 (D9 through D4 are 00h) and a
27 MHz clock at the P
CLK
input. Since all parallel data inputs
are equipped with an internal pull-down device, only those
inputs D0 through D3 which require a logic-1 need be pulled
high.After the Lock_Detect output goes high (true) indicating
the VCO is locked on frequency, TPG_Enable, pin 17, is then
taken to a logic high. TPG_Enable may be temporarily con-
nected to the Lock_Detect output to automate BIST opera-
tion. Test_Output, pin 26, is monitored for a pass/fail indica-
tion. If no errors have been detected, this output will go to a
logic high level approximately 2 field intervals after
TPG_Enable is taken high. If errors have been detected in
the internal circuitry of the CLC020, Test_Output will remain
low until the test is terminated. The BIST is terminated by
taking TPG_Enable to a logic low. Continuous serial data
output is available during the test.
TEST PATTERN GENERATOR
The CLC020 features an on-board
test pattern generator
(TPG)
. Four full-field component video test patterns for both
NTSC and PALstandards, and 4x3 and 16x9 raster sizes are
produced. The test patterns are: flat-field black, PLL patho-
logical, equalizer (EQ) pathological and a modified 75%,
8-color vertical bar pattern. The pathologicals follow recom-
mendations contained in SMPTE RP 178–1996 regarding
the test data used. The color bar pattern does not incorpo-
rate bandwidth limiting coding in the chroma and luma data
when transitioning between the bars. For this reason, it may
not be suitable for use as a visual test pattern or for input to
video D-to-A conversion devices unless measures are taken
to restrict the production of out-of-band frequency compo-
nents.
The TPG is operated by applying the code for the desired
test pattern to D0 through D3 (D4 through D9 are 00h). Since
all parallel data inputs are equipped with an internal
pull-down device, only those inputs D0 through D3 which re-
quire a logic-1 need be pulled high. Next, apply a 27 or
C
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