參數(shù)資料
型號: CLC020
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 消費家電
英文描述: SMPTE 259M Digital Video Serializer with Integrated Cable Driver(SMPTE 259M數(shù)字視頻串行器帶集成電纜驅(qū)動器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 10/15頁
文件大小: 316K
代理商: CLC020
Application Information
A typical application circuit for the CLC020 is shown in Fig-
ure 6 This circuit demonstrates the capabilities of the
CLC020 and allows its evaluation in a variety of configura-
tions. An assembled demonstration board with more com-
prehensive evaluation options is available, part number
SD020EVK. The board may be ordered through any of Na-
tional’s sales offices. Complete circuit board layouts and
schematics, for the SD020EVK are available on National’s
WEB site in the application information for this device. For
latest
information,
www.national.com/appinfo/interface
please
see:
APPLICATION CIRCUIT
Several different input and output drive and loading options
can be constructed on the SD020EVK application circuit
board, Figure 7 Pin headers are provided for input cabling
and control signal access. The appropriate value resistor
packs, 220 and 330
for TTL or 50
for signal sources re-
quiring such loading, should be installed at RP1-4 before ap-
plying input signals. Output loading can be adapted to both
50 and 75
test equipment. Resistors R3 and R4, 24.9
,
size 1206 surface-mount, should be installed when using
50
test loads. Output levels at J1 and J2 will be attenuated
by 3.5 dB under these conditions. (Note: it is necessary to
cut and remove the traces shorting the mounting pads of R3
and R4 before installing these components).
The board’s outputs may be DC interfaced to PECLinputs by
first installing 124
resistors at R1B and R2B, changing R1A
and R2A to 187
and replacing C1 and C2 with short cir-
cuits. The PECL inputs should be directly connected to J1
and J2 without cabling. If 75
cabling is used to connect the
CLC020 to the PECL inputs, the voltage dividers used on the
CLC020 outputs must be removed and re-installed on the
circuit board where the PECL device is mounted. This will
provide correct termination for the cable and biasing for both
the CLC020’s outputs and the PECL inputs. It is most impor-
tant to note that a 75
or equivalent DC loading (measured
with respect to the negative supply rail) must always be in-
stalled at both of the CLC020’s SDO outputs to obtain proper
signal
levels
from
device.
Thevenin-equivalent load circuits, the DC bias applied to the
SDO outputs should not exceed +3V with respect to the
negative supply rail. Serial output levels should be reduced
to 400 mV
p-p
by changing R
REF
to 3.4 k
.
The Test Out output circuit includes a series 453
resistor,
R10, which permits driving 50
test loads. The signal level
at J3 will be attenuated by 20 dB. For high impedance test
loads (
>
500
), replace R10 with a short circuit. If the Lock
Detect output is to be externally monitored, the attached
monitoring circuit should present a DC resistance greater
than 5 k
so as not to affect Lock Detect indicator operation.
When
using
75
DS100917-8
FIGURE 6. Typical Application Circuit
C
www.national.com
10
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