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參數(shù)資料
| 型號： | CLC018 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8 x 8 Digital Crosspoint Switch, 1.4 Gbps(8 x 8數(shù)字交點開關(guān)，1.4 Gbps) |
| 中文描述： | 8 × 8數(shù)字交叉點開關(guān)，1.4吉比特（8 × 8數(shù)字交點開關(guān)，1.4 Gbps）的 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 215K |
| 代理商： | CLC018 |
Electrical Characteristics
(Continued)
(V
CC
= 0V, V
EE
= 5V, V
LL
= 0V; unless otherwise specified) (Note 4).
Parameter
Conditions
Typ
+25C
Min/Max
+25C
Min/Max
40C to
+85C
Units
Signal I/O:
Output Voltage Swing
Output Voltage Range Lower Limit
Output Voltage Range Upper Limit
Control Inputs:
Input Voltage - HIGH
Input Voltage - LOW
Input Voltage - HIGH
Input Voltage - LOW
Input Current - HIGH
Input Current - LOW
MISCELLANEOUS PERFORMANCE
V
CC
Supply Current
R
LOAD
= 75
800
2.5
0
640/960
540/1060
mV
V
V
V
IH min
V
IL max
V
IH min
V
IL max
(Note 3)
(Note 3)
V
LL
= +5V (Note 3)
V
LL
= +5V (Note 3)
V
IH
= V
LL
(Note 3)
V
IL
= V
LL
5V (Note 3)
1
4
4
1
1
100
0.5
4.5
4.5
0.5
0.2/2.0
200/10
0.5
4.5
4.5
0.5
0.1/2.5
250/15
V
V
V
V
μA
μA
All Outputs Active
(Notes 3, 13, 14)
All Outputs TRI-STATE
(Note 3)
V
LL
= 0V (Note 3)
V
LL
= +5V (Note 3)
157
127/202
119/217
mA
V
CC
Supply Current
7
3/11
2/12
mA
V
LL
Supply Current
V
LL
Supply Current
Input Capacitance
Output Capacitance
2.5
7
1.5
2
1.7/3.3
1.5/3.5
mA
mA
pF
pF
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2:
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3:
J-level spec. is 100% tested at +25C.
Note 4:
V
LL
and all V
EE
supply pins are bypassed with 0.01 μF ceramic capacitor.
Note 5:
Bit error rate less than 10
9
over 50% of the bit cell interval.
Note 6:
Measured using a pseudo-random (2
23
1 pattern) binary sequence with all other channels active with an uncorrelated signal.
Note 7:
Spread in propagation delays for all input/output combinations.
Note 8:
Measured between the 20% and 80% levels of the waveform.
Note 9:
Difference in propagation delay for output low-to-high vs. output high-to-low transition.
Note 10:
Refer to the
Configuration Timing Diagram
.
Note 11:
Refer to the
Reset Timing Diagram
.
Note 12:
The bias current for high speed data input depends on the number of data outputs that are selecting that input.
Note 13:
The V
CC
supply current is a function of the number of active data outputs. I
VCC
18*N + 7 mA where N is an integer from 0 to 8.
Note 14:
I
VEE
= I
VCC
+ I
VLL
.
C
www.national.com
3
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