參數(shù)資料
型號: CLC016ACQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Data Retiming PLL with Automatic Rate Selection
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 7/20頁
文件大?。?/td> 422K
代理商: CLC016ACQ
Product Description
The CLC016 Data Retiming PLL is a monolithic circuit that
recovers clock and data from a serial NRZ or NRZI data
stream. The Data Retiming PLL incorporates an Auto-Rate
Selection function which automatically selects one of four
user-configurable data rates. The following outline lists the
material covered in this data sheet:
Typical schematics for +5V or 5.2V operation
Block diagram description
Pin definitions
Design guidelines
Interface connections
Measurement
Typical applications
Printed circuit layout and evaluation boards
For application assistance, refer to the list of telephone num-
bers on the pack page of this data sheet.
Data Retimer Typical Connections
The CLC016 schematics provided in Figure 1 and Figure 2
show typical +5V or 5.2V connections with Auto-Rate Se-
lection configured for SMPTE 259M standard video data
rates: 143, 177, 270 and 360 Mbps. The section
Resistor
Selection for Data Rates
gives tables and equations for de-
termining R
resistor values for any data rate from 50 Mbps
to 400 Mbps. A resistor value table is also given for SONET/
SDH data rates. The schematics in Figure 1 and Figure 2 do
not include input termination. The high impedance inputs on
the CLC016 allow the user to define the termination. The
In-
terfaces
section suggests recommended terminations for
the inputs and outputs of the CLC016.
DS100087-13
FIGURE 1. Typical +5V Connection
DS100087-14
FIGURE 2. Typical 5.2V Connection
7
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