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| 型號(hào)： | CLA78000GCP196 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大小： | 243K |
| 代理商： | CLA78000GCP196 |
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PDS2 - THE GPS ASIC DESIGN SYSTEM
I
Behavioral, Functional, and Gate Level Modelling
I
VHDL and Third Party Links
I
Supports Hierarchical Design Techniques
I
EDIF 2.0 Interface
PDS2 is GPS’s own proprietary ASIC design system. It
provides a fully-integrated, technology independent VLSI
design environment for all GPS CMOS SemiCustom
products.
PDS2 runs on Digital Equipment Computers and is self
configuring according to the available machine resources. It
comprises design capture (schematic capture or VHDL),
testability analysis, logic simulation, fault simulation, auto
place and route, and back annotation. The system offers full
support for hierarchical design techniques, maintained from
design capture through to layout, as well as advanced design
management tools. PDS2 may be used either at a GPS
Design Center or under licence at the customer’s premises. A
three day training course is available for first time users.
THIRD PARTY SOFTWARE SUPPORT
I
Design Kits for major industry standard ASIC design
software tools
I
All libraries include fully detailed timing information
I
EDIF 2.0 Interface
I
Post layout back annotation available
GPS supports a wide range of third party design tools
including IKOS, Mentor, Verilog, and Viewlogic at the time of
printing. Please check with our Sales Offices for the most
recent additions. The design kits offer fully detailed timing
information for all cell libraries, netlist extraction utilities, and
post layout back annotation capability where applicable. An
example of a workstation design flow is shown in fig 5 below.
Please contact your local GEC Plessey Semiconductor’s
sales office for further information about support of particular
tools.
Fig 5. Workstation Design Flow
SPECIFICATIONS
THERMAL MANAGEMENT
I
Lower power CMOS for better thermal management
I
Improved reliability
I
Power packages available
The increase in speed and density available through
CMOS process geometry reduction, results in a
corresponding increase in power dissipation. SemiCustom
designers now have the ability to design circuits of 100,000
gates and over, and chip power consumption is (or should be)
a very important concern.
The logic core of 100K plus gates is the dominant factor
in power dissipation at this complexity. It is essential to offer
ultra low power core logic to maintain an acceptable overall
chip power budget.
To minimize this problem GPS’s CLA70000 arrays offer
low power factors and a selection of power packages.
Dissipation of 5
μ
W per gate per Mhz gate power and 1
μ
W per
gate load, is lower than most competitive arrays, with the
reduced junction temperatures having the added advantage
of improved performance and reliability.
CLA70000 POWER DISSIPATION CALCULATION
CLA70000 series power dissipation for any array can be
estimated by following the example (calculated for the CLA76XXX)
below.
Number of available gates
Assume percent gates used
Number of used gates (110102 X 0.4)
Assume 15% of gates switching during.
each clock cycle (44045 X 0.15)
Power dissipation/gate/Mhz
(gate fanout typically 2 loads)
110112
40%
44045
6607
7
μ
W
Total core dissipation/Mhz (6607 X 0.007)
46.2 mW
Number of available I/O pads
200
Percent of I/O pads used as Outputs
Number of I/O pads used as Outputs
Number of output buffers switching
each clock cycle (20%)
40%
80
16
Dissipation/output buffers/Mhz/pF
Output loading
25
μ
W
50 pF
Power/output buffer/Mhz
Total output buffer dissipation/Mhz
1.25mW
20mW
Total Power dissipation/Mhz
66.2mW
Estimated dissipation of the circuit at the frequencies below is
Total Power at 10 Mhz clock rate
Total Power at 25Mhz clock rate
0.66W
1.65W
Schematic
Capture
Test Vector
Generation
Simulation
Vector
Translation
Back -
Annotation
ERC &
Netlist
Translation
Schematic
Symbols
CLA
Libraries
Simulation
Models
MLE
Place &
Route
Design
Verification
Test Program
Generation
PDS
WORKSTATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLA78000GCP256 | ASIC |
| CLA70000 | ASIC |
| CLA74000 | ASIC |
| CLA76000 | ASIC |
| CLA77000 | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLA78000GCP256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA80000-SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA80E1200HF | 功能描述:SCR模塊 High Efficiency Single Thryistor RoHS:否 制造商:Vishay Semiconductors 開(kāi)啟狀態(tài) RMS 電流 (It RMS):260 A 不重復(fù)通態(tài)電流:4000 A 最大轉(zhuǎn)折電流 IBO:4200 A 額定重復(fù)關(guān)閉狀態(tài)電壓 VDRM:1.6 kV 關(guān)閉狀態(tài)漏泄電流（在 VDRM IDRM 下）:20 mA 開(kāi)啟狀態(tài)電壓:1.43 V 保持電流（Ih 最大值）: 柵觸發(fā)電壓 (Vgt): 柵觸發(fā)電流 (Igt): 最大工作溫度:+ 150 C 安裝風(fēng)格:Chassis 封裝 / 箱體:INT-A-PAK |
| CLA80MT1200NHB | 功能描述:THYRISTOR PHASE TO247-3 制造商:ixys 系列:DT-Triac? 包裝:管件 零件狀態(tài):有效 三端雙向可控硅類型:標(biāo)準(zhǔn) 電壓 - 斷態(tài):1200V（1.2kV） 電流 - 通態(tài)（It（RMS））（最大值）:88A 電壓 - 柵極觸發(fā)（Vgt）（最大值）:1.7V 電流 - 不重復(fù)浪涌 50，60Hz（Itsm）:480A，520A 電流 - 柵極觸發(fā)（Igt）（最大值）:70mA 電流 - 保持（Ih）（最大值）:70mA 配置:單一 安裝類型:通孔 封裝/外殼:TO-247-3 供應(yīng)商器件封裝:TO-247-3 標(biāo)準(zhǔn)包裝:30 |
| CLA80MT1200NHR | 功能描述:THYRISTOR PHASE ISO247 制造商:ixys 系列:DT-Triac? 包裝:管件 零件狀態(tài):有效 三端雙向可控硅類型:標(biāo)準(zhǔn) 電壓 - 斷態(tài):1200V（1.2kV） 電流 - 通態(tài)（It（RMS））（最大值）:88A 電壓 - 柵極觸發(fā)（Vgt）（最大值）:1.7V 電流 - 不重復(fù)浪涌 50，60Hz（Itsm）:480A，520A 電流 - 柵極觸發(fā)（Igt）（最大值）:70mA 電流 - 保持（Ih）（最大值）:70mA 配置:單一 安裝類型:通孔 封裝/外殼:TO-247-3 供應(yīng)商器件封裝:ISO247 標(biāo)準(zhǔn)包裝:30 |
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