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| 型號： | CLA72000 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 105K |
| 代理商： | CLA72000 |
CLA70000V
5
PDS2 - THE GPS ASIC DESIGN SYSTEM
I
Behavioral, Functional, and Gate Level Modelling
I
VHDL and Third Party Links
I
Supports Hierarchical Design Techniques
I
EDIF 2.0 Interface
PDS2 is GPS’s own proprietary ASIC design system. It
provides a fully-integrated, technology independent VLSI
design environment for all GPS CMOS SemiCustom
products.
PDS2 runs on Digital Equipment computers and is self
configuring according to the available machine resources. It
comprises design capture (schematic capture or VHDL),
testability analysis, logic simulation, fault simulation, auto
place and route, and back annotation. The system offers full
support for hierarchical design techniques, maintained from
design capture through to layout, as well as advanced design
management tools. PDS2 may be used either at a GPS
Design Center or under licence at the customer’s premises. A
three day training course is available for first time users.
THIRD PARTY SOFTWARE SUPPORT
I
Design Kits for major industry standard ASIC design
software tools
I
All libraries include fully detailed timing information
I
EDIF 2.0 Interface
I
Post layout back annotation available
GPS supports a wide range of third party design tools
including IKOS, Mentor, Verilog, and Viewlogic. The design
kits offer fully detailed timing information for all cell libraries,
netlist extraction utilities, and post layout back annotation
capability where applicable. An example of a workstation
design flow is shown in the figure 5 (opposite). Please contact
your local GEC Plessey Semiconductor’s sales office for
further information about support of particular tools.
Schematic
Capture
Test Vector
Generation
Simulation
Vector
Translation
Back -
Annotation
ERC &
Netlist
Translation
Schematic
Symbols
LiCLA
Simulation
Models
MLE
Place &
Route
Design
Verification
Test Program
Generation
PDS
WORKSTATION
Figure 5 : Workstation Design Flow
DESIGN SUPPORT
Design support is available from various centres worldwide
each of which is connected to our Headquarters via high
speed data links. A design centre engineer is assigned to
each customers circuit, to ensure good communication, and a
smooth and efficient design flow.
As part of the design process GPS operates a thorough design
audit procedure to verify compliance with customer specifica-
tion and to ensure manufacturability. The procedure includes
four separate review meetings, with the customer, held a key
stages of the design. The standard design audit procedure is
outlined opposite.
Review 1:
Held at the beginning of the design cycle to
check and agree on specifications and design
timescales.
Held after Logic Simulation and prior to Layout.
Checks to ensure satisfactory functionality, tim-
ing performance, and adequate fault coverage
Held after Layout and Post layout Simulation.
Verification of design performance after inser-
tion of actual track loads. Final check of all
device specifications before prototype manu-
facture.
Held after prototype delivery. Confirms that the
devices meet the specification and are suitable
for full scale production.
Review 2
Review 3
Review 4
DESIGN TOOLS
The focus of the GEC Plessey design tool methodology is that of maintaining an open CAD system with all interfaces standardized
via EDIF 2.0 . This enables us to provide full support for a variety of 3rd party ASIC design tools and facilitates rapid updating
of associated libraries. It also provides an interface to the GEC Plessey (PDS2) design system, which offers a total design
environment including behavioral and functional level modelling.
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