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參數(shù)資料
| 型號(hào)： | CLA72000 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | CLA72000 |
CLA70000V
2
VSS
Supply
VSS
Supply
Programmable
contacts
Figure 1 : Process ‘VQ’ Process Cross Section
CORE CELL DESIGN
A four transistor group (2 NMOS and 2PMOS) (fig 2.) forms the
basic cell of the core array. This array element is repeated in
a regular fashion over the complete core area to give a
homogeneous ‘Full Field’ (sea of gates) array. This lends itself
to hierarchical design, allowing pre-routed user defined
subcircuits to be repeated anywhere on the array. The core
cell structure has been carefully designed to maximise the
number of nets which may be routed through the cell. This
enables optimal routing for both data flow and control signal
distribution schemes thus giving very high overall utilisation
figures. This feature is of particular benefit in designs using
highly structured blocks such as memory or arithmetic
functions.
Figure 2 : Diagrammatic representation of Array Core Cell
IP
OP1
OP2
IB1 IB2
Bonding
Pad
I/O BLOCK
IB3 IB4 IB5
CMOS PROCESS TECHNOLOGY
The CLA70000 arrays are based on GEC Plessey
Semiconductors well proven 1
μ
CMOS process,
manufactured at GPS’s advanced , Class 10, six-inch wafer
fabrication facility. The process (fig.1) is a twin well, self
aligned oxide-isolated technology, with an effective channel
length of 0.8
μ
m (1.0
μ
m drawn ), giving a low defect density,
high reliability, and inherently low power dissipation. The
process has excellent immunity to latch-up, and ESD, and
exhibits stable performance characteristics.
INPUT/OUTPUT BUFFER DESIGN
The peripheral cells (fig.3) are fully programmable as Input,
Output, VDD or GND, and they are designed to offer several
interfacing options, TTL and CMOS for example. The cells
already contain input ‘pull-up’ and ‘pull-down’ resistors and
Electro Static Discharge protection elements. Components
for implementing Schmitt Triggers, TTL threshold detectors,
tristate control, and flip-flops for signal re-timing are also
included. A range of output buffers is available with various
output drive currents to match system requirements.
Noise transients due to a large number of simultaneously
switching outputs are an increasing problem as bus widths
widen (The supply pad location, and the inductance of the
bond wires and package leads are also factors). CLA70000
Arrays offer several I/O buffers with the capability to control the
output slew (di/dt) (fig.4) which are invaluable in controlling
these transients when driving large capacitive loads such as
busses.
PIN
OPT3
N
P
P
N
D
INPUT
DATA
2.5 Volts
2.5 Volts
50 pF
IBSK1, IBSK2 and IBSK3 have been characterised
to give the correct timing when connected to the OPT* cells.
slew rate
controlled
driver
SLEW RATE CONTROL
Figure 3
Figure 4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLA73000 | ASIC |
| CLA75000 | ASIC |
| CLA78000 | ASIC |
| CLA80000-SERIES | ASIC |
| CLA864 | NPN-OUTPUT DC-INPUT OPTOCOUPLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLA72000AC68 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA72000AC84 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA72000DC24 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA72000DC28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLA72000DC40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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