參數(shù)資料
型號(hào)： CL-PS6700
廠商： Cirrus Logic, Inc.
英文描述： Low-Power PC Card Controller for the CL-PS7111
中文描述： 低功耗PC卡控制器的CL - PS7111
文件頁(yè)數(shù)： 13/48頁(yè)
文件大?。?/td> 562K
代理商： CL-PS6700
November 1997
13
PRELIMINARY DATA BOOK v1.0
PIN DESCRIPTIONS
C
I R R U S
L
O G I C
C
O N F I D E N T I A L
, N D A R
E Q U I R E D
CL-PS6700
Low-Power PC Card Controller
PDREQ_L/
GPIO
I/O
sys
PC Card DMA Request:
When configured as PDREQ_L, this wire-OR’ed signal indicates to the
CL-PS7111 that one of the PC Card sockets has issued a DMA request. Since this is shared by all
PC Card sockets, the system should enable DMA to only one socket at a time and program the
CL-PS7111 DMA routine.
General-Purpose I/O:
When configured as GPIO, this signal can be used as an input capable of
generating an interrupt. As a general-purpose output, it is actively driven in both output states, high
and low.
2.1.3
Interrupt and Abort Signals
Signal
Type
Power
SourceDescription
PIRQ_L[1:0] OD-O
sys
PC Card Interrupt Request:
The interrupt request lines can be wire-OR’ed if there are two
CL-PS6700 controllers. It signals that one or two CL-PS6700s have an interrupt pending. The
exact source of pending interrupts can be read in a CL-PS6700 Interrupt Source register. Exter-
nal pull-up resistors for these signals are required. Alternatively, every interrupt request line can
be connected to one of the CL-PS7111 active-low interrupt inputs.
2.1.4
Clock, Reset, and Sleep Signals
Signal
Type
Power
SourceDescription
PCLK
I
sys
All transfers between the CL-PS7111 and the CL-PS6700 are synchronous to this clock signal. To
conserve power, PCLK can be disabled when the PC Card subsystem is not in use.
RESET_L
I
sys
This reset signal can be driven by one of the GPIO outputs of the CL-PS7111 or by a system
reset. It is an active-low input and places all CL-PS6700 registers and outputs in their default
power-up/reset condition.
PSLEEP_L
I
sys
The CL-PS7111 drives this signal either by the RUN output or by any GPIO. This active-low signal
is synchronous to the rising edge of PCLK. PSLEEP_L causes the CL-PS6700 to complete or
abort (as configured) any card operation in progress, enter the lowest power mode, and disable
its I/O according to the
Table 4-2 on page 32
. The CL-PS7111 can discontinue transactions to
CL-PS6700 before asserting PSLEEP_L; if a card transaction in progress or in the queue is lost
due to PSLEEP_L being asserted, an interrupt (RD_FAIL or WR_FAIL) is generated. There must
be two PCLKs after PSLEEP_L is asserted to go into Standby mode.
2.1.2
Access Control Signals
(cont.)
Signal
Type
Power
SourceDescription
相關(guān)PDF資料
PDF描述
CL-PS6700-VC-A Low-Power PC Card Controller for the CL-PS7111
CL-PS7110-VC-A Low-Power System-on-a-Chip
CL-PS7110-VI-A Low-Power System-on-a-Chip
CL-PS7110 Low-Power System-on-a-Chip
CL-PS7111 Low-Power System-on-a-Chip
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CL-PS6700-VC-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power PC Card Controller for the CL-PS7111
CL-PS7110 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip
CL-PS7110-VC-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip
CL-PS7110-VI-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip
CL-PS7111 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip
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