
CHRONTEL
DAC Control Register
CH7301A
DC
22
201-0000-036 Rev 1.1, 3/20/2000
Symbol:
Address:
21h
Bits:
6
Bit 0 of register DC selects the DAC bypass mode. A value of ‘1’ outputs the incoming data directly at the
DAC[2:0] outputs.
Bits 2-1 of register DC control the DAC gain. DACG0 should be set low for NTSC and PAL-M video standards,
and high for PAL and NTSC-J video standards. DACG1 should be low when the input data format is RGB (IDF =
0-3), and high when the input data format is YCrCb (IDF = 4).
Bits 4-3 of register DC select the signal to be output from the C/H Sync pin according to
Table 9
below.
Buffered Clock Output Register
Symbol:
Address:
BCO
22h
Bits:
8
Bits 2-0 of register BCO select the signal output at the BCO pin, according to
Table 10
below:
Bit 3 of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the output
pad.
Bit 4 of register BCO enables the BCO output. When BCOEN is high, the BCO pin will output the selected signal.
When BCOEN is low, the BCO pin will be held in tri-state mode.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved
TYPE:
R/W
DEFAULT:
SYNCO1 SYNCO0
R/W
0
DACG1
R/W
DACG0
R/W
DACBP
R/W
R/W
R/W
0
0
0
0
0
0
Table 9: Composite / Horizontal Sync Output
SYNCO[1:0]
C/H Sync Output
00
No Output
01
VGA Horizontal Sync
10
TV Composite Sync (Not Valid)
11
TV Horizontal Sync (Not Valid)
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved
TYPE:
R/W
DEFAULT:
0
BCOEN
R/W
BCOP
R/W
BCO2
R/W
BCO1
R/W
BCO0
R/W
R/W
R/W
0
0
0
0
0
0
0
Table 10: BCO Output Signal
BCO[2:0]
Buffered Clock Output
000
(Not Valid)
001
(Not Valid)
010
(Not Valid)
011
(Not Valid)
BCO[2:0]
100
101
110
111
Buffered Clock Output
(Not Valid)
(Not Valid)
VGA Vertical Sync
(Not Valid)