參數(shù)資料
型號(hào)： CH7301A
廠商： Electronic Theatre Controls, Inc.
英文描述： Chrontel CH7301 DVI Output Device
中文描述： 昆泰CH7301 DVI輸出設(shè)備
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 485K
代理商： CH7301A
201-0000-036 Rev 1.1, 3/20/2000
17
CHRONTEL
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be
written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle
is shown in
Figure 11
.
CH7301A
.
Note:
The acknowledge is from the CH7301 (slave).
Figure 11: Auto-Increment Write Cycle
During auto-increment mode transfers, the register address pointer continues to increment for each write cycle until
AR[6:0] = 4F. The next byte of information represents a new auto-sequencing “Starting address”, which is the
address of the register to receive the next byte. The auto-sequencing then resumes based on this new “Starting
address”. The auto-increment sequence can be terminated any time by either a “STOP” or “RESTART” condition.
The write operation can be terminated with a “STOP” condition.
CH7301 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7301 releases the data
line to allow the master to generate the STOP condition or the RESTART condition.
To read the content of the registers, the master device starts by issuing a “START” condition (or a “RESTART”
condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB
with AR[6:0], containing the address of the register that the master device intends to read from in AR[6:0]. The
master device should then issue a “RESTART” condition (“RESTART” = “START”, without a previous “STOP”
condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the
master’s intention to read data hereafter. The master then reads the next byte of data (the content of the register
specified in the RAB). For alternating modes, another RESTART condition, followed by another DAB with R/W =
0 and RAB, is expected from the master device. The master device then issues another RESTART, followed by
another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition,
followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read
events. Two consecutive alternating read cycles are shown in
Figure 12
.
SD
SC
1 - 8
9
RAB n
ACK
Start
Condition
Stop
Condition
CH7301
acknowledge
1 - 8
Data n
9
1 - 8
9
ACK
Data n+1
ACK
CH7301
acknowledge
CH7301
acknowledge
CH7301
acknowledge
1 - 7
Device ID
8
R/W*
9
ACK
I
2
C
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