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參數(shù)資料
| 型號： | CH7203 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MPEG to TV Encoder with 16-bit Input |
| 中文描述： | 電視的MPEG編碼器，16位輸入 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 108K |
| 代理商： | CH7203 |
CHRONTEL
CH7203
6
201-0000-031 Rev 2.0, 6/2/99
General Description
The CH7203 is a fully integrated solution for converting 16-bit YCrCb (4:2:2) digital video inputs into high-
quality NTSC or PAL video signals while generating all essential clock signals for MPEG playback. All
essential circuitry for this conversion and clock generation (Dual PLL’s, linear interpolator, digital filters,
NTSC/PAL encoder, DAC’s) are contained in the CH7203 making it an essential component of any low-cost
solution for video-CD playback machines. Refer to the Block Diagram on page 1 and the Interface Diagram on
page 5.
Functional Description
The encoded luminance (Y) and color-difference (U,V) are interpolated, and filtered through digital filters to
minimize aliasing problems. The filtered signals go to the digital encoder where they are transformed to
composite and S-video outputs, and then they are converted by the three 9-bit DACs to analog outputs.
16-bit YCrCb (4:2:2) Input
Y data is input through the Y[7:0] inputs and CrCb data is multiplexed through the C[7:0] inputs. When
CRSEN* = 1, the Cr Select input, CRS, is ignored, and all even horizontal pixels are Cb data and all odd
horizontal pixels are Cr. Refer to
Figure6
on page 7 for the definition of “even” and “odd” pixels. When
CRSEN* = 0, the alternating CRS signal specifies the CrCb sequence. CRS = 1 indicates C[7:0] carries Cr
data, and CRS = 0 indicates C[7:0] carries Cb data.
Clock/Data/Synchronization Timing
The CH7203 not only works as an NTSC/PAL encoder, it also supplies the necessary clocks (1X pixel, 2X
pixel, video system, and audio) and synchronization (HSYNC* and VSYNC*) signals to other building blocks
in the video system. For this reason, the CH7203 works
only
in the Master mode.
It is important to note the CH7203 does not have a “pixel clock” input pin. Therefore, the timing issues related
to video pixel data being supplied from, for example, the MPEG decoder, to the CH7203 (pins Y[7:0] and
C[7:0]) need to be clarified. Assume the pixel synchronization of a system is based on the 2X pixel clock
(2XPLCK). In this type of design, 2XPCLK is distributed across the entire video system, and it is also used to
latch the incoming data appearing at pins Y[7:0] and C[7:0].
Figure 7
on page 8 shows all timing referenced
to the 2XPCLK output signal (loaded with 50pF).
Video Encoder Modes
Combinations of the two signals MOD1 and MOD0 select the various power saving modes as shown below.
Table 3 Video Encoder Modes
Frequency Select Modes
The frequency select input FS affects the DCLK and ACLK outputs as shown below:
FS = 1 (default) DCLK = 40.5 MHz, ACLK = 16.934 MHz
FS = 0
DCLK = 33.9 MHz, ACLK = 11.289 MHz
MOD1
MOD0
Video Encoder Mode
1
1
NTSC
1
0
PAL
0
1
PAL-60
0
0
Sleep mode (Encoder off,both PLLs running)
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