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參數(shù)資料
| 型號： | CH7203 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MPEG to TV Encoder with 16-bit Input |
| 中文描述： | 電視的MPEG編碼器，16位輸入 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 108K |
| 代理商： | CH7203 |
CHRONTEL
CH7203
4
201-0000-031 Rev 2.0, 6/2/99
Table 2. Pin Descriptions (continued)
Pin
Type
Symbol
Description
19-26
In
Y[7:0]
Video Input
These pins accept the “Y” data of the YCrCb (4:2:2) digital video
format. For more details, please refer to the timing diagram
shown in
Figure 7
on page 8. Y has a nominal range of 16-235.
28
In
RSET
Reference Resistor
A 360
resistor with short and wide traces should be attached
between RSET and ground. No other connections should be
made to this pin.
30
Out
C
Chrominance Output
A 75
termination resistor with short traces should be attached
between C and ground for optimum performance.
31
Out
CVBS
Composite Output
A 75
termination resistor with short traces should be attached
between CVBS and ground for optimum performance.
32
Out
Y
Luminance Output
A 75
termination resistor with short traces should be attached
between Y and ground for optimum performance.
33, 34, 40, 44
Power
GND
Digital Ground
These pins provide the ground reference for the digital section of
the CH7203. These pins MUST be connected to the system
ground through
independent
ground vias.
35
Out
HSYNC*
Horizontal Sync Output
The horizontal sync output is generated by the CH7203 for master
mode operation. HSYNC* is an active low signal with a 5V output
swing. For additional information, please refer to the timing
diagrams shown in
Figures 5
and
6
on page 7.
37
Out
VSYNC*
Vertical Sync Output
The vertical sync output is generated by the CH7203 for master
mode operation. VSYNC* is an active low signal with a 5V output
swing. For additional information, please refer to the timing
diagrams shown in
Figures 5
and
7
on page 7 and 8.
38
In
MOD0
Mode bit 0
- internally pulled-up
This input works in conjunction with the MOD1 input to select
NTSC, PAL, or Sleep Mode functions. Refer to
Table 3, “Video
Encoder Modes,” on page 6
for details.
39
Out
PCLK
Video Pixel Clock Output
13.5 MHz clock output. The output swing is 5V.
41
Out
DCLK
MPEG Decoder Clock Output
40.5 MHz or 33.9 MHz clock output (selectable by FS). The output
swing is 5V.
43
Out
2XPCLK
Double Pixel Clock Output
27 MHz clock output. The output swing is 5V.
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相關(guān)代理商/技術(shù)參數(shù) |
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| CH7203-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MPEG to TV Encoder with 16-bit Input |
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| CH721C276MA80A8 | 制造商:AVX Corporation 功能描述: |
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| CH723 | 制造商:Hubbell Wiring Device-Kellems 功能描述:WALLPLATE, 1-G, 2.15 OPENING, CHR PLT |
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