
201-0000-042 Rev. 1.1, 9/29/2000
37
CHRONTEL
CH7012A
Bit 3 of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the output
pad.
Bit 4 of register BCO enables the BCO output. When BCOEN is high, the BCO pin will output the selected signal.
When BCOEN is low, the BCO pin will be held in tri-state mode.
Bits 7-5 of register BCO select the K3 divider, according to
Table 21
below.
Test Pattern Register
Symbol:
TSTP
Address:
48h
Bits:
5
Bits 1-0 of register TSTP control the test pattern generation block. The pattern generated is determined by
Table 22
below.
Bit 2 of register TSTP is a test control, and should be left at the default value.
Bit 3 of register TSTP controls the datapath reset signal. A value of ‘0’ holds the datapath in a reset condition,
while a value of ‘1’, places the datapath in normal mode. The datapath is also reset at power on by an internally
generated power on reset signal.
Bit 4 of register TSTP controls the
serial port
reset signal. A value of ‘0’ holds the
serial port
registers in a reset
condition, while a value of ‘1’, places the
serial port
registers in normal mode. The
serial port
registers are also reset
at power on by an internally generated power on reset signal.
Table 21: K3 Selection
SHF[2:0]
000
001
010
011
100
101
110
111
K3
2.5
3.0
3.5
4.0
4.5
5.0
6.0
7.0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
ResetIB ResetDB
R/W
1
RSA
R/W
TSTP1
R/W
TSTP0
R/W
R/W
1
0
0
0
Table 22: Test Pattern Control
TSTP[1:0]
Buffered Clock Output
00
No test pattern – Input data is used
01
Color Bars
1X
Horizontal Luminance Ramp