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參數(shù)資料
| 型號(hào)： | CH7012A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7012 TV Output Device |
| 中文描述： | 昆泰CH7012電視輸出設(shè)備 |
| 文件頁數(shù)： | 27/42頁 |
| 文件大?。?/td> | 551K |
| 代理商： | CH7012A |
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201-0000-042 Rev. 1.1, 9/29/2000
27
CHRONTEL
Start of Active Video Register
CH7012A
SAV
Symbol:
Address:
04h
Bits:
8
Register SAV controls the delay, in pixel increments, from leading edge of horizontal sync to start of active video.
The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the Text
Enhancement register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between
0 and 511 pixels. Therefore, in any 2X clock mode the number of 2X clocks from the leading edge of sync to the
first active data must be a multiple of two clocks.
Horizontal Position Register
Symbol:
HP
Address:
05h
Bits:
8
Register HP is used to shift the displayed TV image in a horizontal direction ( left or right) to achieve a horizontally
centered image on screen. The entire bit field, HP[8:0], is comprised of this register HP[7:0] plus the MSB value
contained in the Text Enhancement register, bit HP8. Increasing values move the displayed image position right, and
decreasing values move the image position left.
Vertical Position Register
Symbol:
VP
Address:
06h
Bits:
8
Register VP is used to shift the displayed TV image in a vertical direction ( up or down) to achieve a vertically
centered image on screen. The entire bit field, VP[8:0], is comprised of this register HP[7:0] plus the MSB value
contained in the Text Enhancement register, bit VP8. The value represents the TV line number (relative to the VGA
vertical sync) used to initiate the generation and insertion of the TV vertical interval (i.e. the first sequence of
equalizing pulses). Increasing values delay the output of the TV vertical sync, causing the image position to move
up on the TV screen. Decreasing values, therefore, move the image position DOWN. Each increment moves the
image position by one TV lines (approximately 2 input lines). The maximum value that should be programmed
into the VP[8:0] value is the number of TV lines per field minus one half (262 or 312). When panning the image up,
the number should be increased until (TVLPF-1/2) is reached, the next step should be to reset the register to zero.
When panning the image down the screen, decrement the VP[8:0] value until the value zero is reached. The next
step should set the register to TVLPF-1/2, and then decrement for further changes.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
SAV7
R/W
SAV6
R/W
SAV5
R/W
SAV4
R/W
SAV3
R/W
SAV2
R/W
SAV1
R/W
SAV0
R/W
0
1
0
1
0
0
0
0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
HP7
R/W
HP6
R/W
HP5
R/W
HP4
R/W
HP3
R/W
HP2
R/W
HP1
R/W
HP0
R/W
0
1
0
1
0
0
0
0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
VP7
R/W
VP6
R/W
VP5
R/W
VP4
R/W
VP3
R/W
VP2
R/W
VP1
R/W
VP0
R/W
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CH7012A-T | Chrontel CH7012 TV Output Device |
| CH7202 | MPEG to TV Encoder with 8-bit Input |
| CH7203 | MPEG to TV Encoder with 16-bit Input |
| CH7203-V | MPEG to TV Encoder with 16-bit Input |
| CH7301A | Chrontel CH7301 DVI Output Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CH7012A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7012 TV Output Device |
| CH7013A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
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