
2000 Nov 28
4
Philips Semiconductors
Preliminary specification
GSM/DCS/PCS power amplifier
CGY2014ATW
PINNING
SYMBOL
PIN
DESCRIPTION
n.c.
RFI(HB)
V
DD1(HB)
V
DD2(HB)
V
DD2(HB)
V
DD2(LB)
V
DD1(LB)
GND1(LB)
RFI(LB)
n.c.
V
GLB
n.c.
RFO/V
DD3(LB)
RFO/V
DD3(LB)
GND
n.c.
RFO/V
DD3(HB)
RFO/V
DD3(HB)
n.c.
V
GHB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
not connected
DCS/PCS power amplifier input
DCS/PCS first stage supply voltage
DCS/PCS second stage supply voltage
DCS/PCS second stage supply voltage
GSM second stage supply voltage
GSM first stage supply voltage
GSM first stage ground
GSM power amplifier input
not connected
GSM power amplifier gates
not connected
GSM power amplifier output and third stage supply voltage
GSM power amplifier output and third stage supply voltage
ground
internal connection to ground; pin should not be connected to the board
DCS/PCS power amplifier output and third stage supply voltage
DCS/PCS power amplifier output and third stage supply voltage
not connected
DCS/PCS power amplifier gates
ground
exposed die
FUNCTIONAL DESCRIPTION
Operating conditions
The CGY2014ATW is designed to meet the European
Telecommunications Standards Institute (ETSI) GSM
documents, the “ETS 300 577 specification” which are
defined as follows:
t
on
= 570
μ
s
T = 4.16 ms
Duty cycle
δ
=
1
/
8
.
Multislot operation can be implemented provided that the
application circuit does not drive the IC beyond the limiting
values.
Power amplifier
The GSM and DCS/PCS power amplifiers consist of three
cascaded gain stages with an open-drain configuration.
Each drain has to be loaded externally by an adequate
reactive circuit which also has to be a DC path to the
supply.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
FCA197
CGY2014ATW
n.c.
RFI(HB)
VDD1(HB)
VDD2(HB)
VDD2(HB)
VDD2(LB)
VDD1(LB)
GND1(LB)
RFI(LB)
n.c.
VGHB
n.c.
RFO/VDD3(HB)
RFO/VDD3(HB)
n.c.
GND
RFO/VDD3(LB)
RFO/VDD3(LB)
n.c.
VGLB
Fig.2 Pin configuration.