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參數(shù)資料
| 型號(hào)： | CDRM622 |
| 廠商： | Lineage Power |
| 英文描述： | 622 Mbits/s Multichannel Digital Timing Recovery(622M位/秒 多通道數(shù)字定時(shí)恢復(fù)) |
| 中文描述： | 622 Mbits /秒多通道數(shù)字定時(shí)恢復(fù)（622M位/秒多通道數(shù)字定時(shí)恢復(fù)） |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 278K |
| 代理商： | CDRM622 |
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CDRM622
622 Mbits/s Multichannel Digital Timing Recovery Macrocell
Data Sheet
June 1999
4
Lucent Technologies Inc.
Hardware Interface
Low-Speed 77.76 Mbytes/s Interface
The internal timing performance of the macrocell is independent of the remaining device logic with the exception of
the low-speed interface. The macrocell sources clock and data bytes for each channel to be captured and pro-
cessed by the device logic. In the other direction, the device logic sources data bytes to be captured and processed
by the macrocell. These interfaces are generally designed and verified using static timing analysis. Figure 2 illus-
trates these interfaces and their associated timing.
Input Capacitance
For all digital inputs, the input capacitance at the boundary of the macrocell is 0.02 pF.
Output Signal Drive Strength
For all low-speed outputs, the output driver strength is equivalent to that of a Lucent-type SBNS standard cell. (See
HL250C 3.3 Volt 0.25 μm CMOS Standard-Cell Library System ASIC Data Book March 1998 (MN97-066ASIC)).
Table 1. Functional Signals
Signal Name
Type
Description
HDIN[(n – 1):0]
LD[(n – 1):0]R[7:0]
LCKR[(n – 1):0]
LCK78
I
622.08 Mbits/s serial data inputs. One input for each independent data channel.
Low-speed demultiplexed data bytes retimed to recovered 77.76 MHz clocks.
Low-speed 77.76 MHz recovered clocks.
Low-speed (77.76 MHz) PLL divide-down clock. Can be used as a PLL activity
monitor point. This buffered version of internal transmit 77.76 MHz clock can be
used to time data transfer into the transmitter.
77.76 MHz data byte inputs to transmitter.
622.08 Mbits/s serial data outputs.
77.76 MHz reference clock input to clock synthesizer.
Connects to external 10 k
±
1% resistor that is tied to ground potential (V
SSA
)
on the circuit pack. Provides reference current to on-chip PLL.
(Active-High).
Asynchronous master reset for macrocell initialization. Also used
in test mode to reset test circuitry.
(Active-High).
PLL powerdown for I
DDQ
testing.
(Active-High).
Per-channel powerdown of receiver.
O
O
O
LDAT[(n – 1):0]X[7:0]
HDOUT[(n – 1):0]
REF78
REXT
I
O
I
I
MRESET
I
PLLPWRDN
RXPWRDN[(n – 1):0]
I
I
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