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參數(shù)資料
| 型號： | CDRM622 |
| 廠商： | Lineage Power |
| 英文描述： | 622 Mbits/s Multichannel Digital Timing Recovery(622M位/秒 多通道數(shù)字定時(shí)恢復(fù)) |
| 中文描述： | 622 Mbits /秒多通道數(shù)字定時(shí)恢復(fù)（622M位/秒多通道數(shù)字定時(shí)恢復(fù)） |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 278K |
| 代理商： | CDRM622 |
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery Macrocell
Data Sheet
June 1999
10
Lucent Technologies Inc.
Test Interface
(continued)
High-Speed Loopback
The output of the transmitter can be looped back into the receiver. This feature enables factory testing 622 Mbits/s
circuitry on a test set only capable of 200 MHz clocking. System product diagnostics may also find a use for this
mode. The loopback function can be selected on a per-channel basis or by a global override.
CDR Testing
Built-in test cirtuitry is included as part of the macrocell in order to ensure quality of manufacture. Test access and
control has been added to facilitate characterization and evaluation of the macrocell function. Macrocell testing is
added by Lucent to verify PLL, high-speed data paths, and fault coverage within the macrocell.
One such test configures the macrocell in high-speed loopback with transmit pattern generation and receive byte
alignment in order to observe 77.76 Mbytes/s data after passing through both transmitter and receiver at
622.08 Mbits/s. This test requires only the PLL reference clock to be sourced from the factory test set.
Also, each of the recovered channels (clock and data byte) can be brought out through the test port one channel at
a time, and the synthesized clock, divided by eight, is brought out for frequency measurement and evaluation.
Macrocell testing is set up by an internal control register that is written through a 3-pin serial test interface.
Built-in testing cannot verify the 78 MHz interface connections to the device logic. Therefore, at least one test exer-
cising the functional data path through the macrocell using PLL bypass is required from the device logic designers.
Test Access
In order to accomplish these tests, access is required to approximately 20 test signals through the device pins. Test
pins can be multiplexed with other pins and TSTMODE = 1 can be used as an indication when CDR test access is
needed. In addition, to standard manufacture testing, access to built-in test features has been useful during func-
tional board-level prototype prove-in.
CDR testing requires access to the following signals
from the device pins
: TSTMODE, BYPASS, TSTCLK,
RESETRN, RESETTN, TSTSHFTLD, ECSEL, EXDNUP ETOGGLE, LOOPBKEN, TSTPHASE, TSTMUX[8:0].
REF78, MRESET, and HDIN[(n – 1):0] are also used during testing but are expected to be controllable through
functional device pins. REF78 should be controllable through the reference clock input to the device. A 155 MHz
reference clock pin which is divided on-chip to 78 MHz is acceptable. MRESET should be controllable through the
device powerup reset pin.
Table 4. CDR Test Signals
Signal Name
Type
Description
TSTMODE
TSTSHFTLD
I
I
(Active-High).
Enables CDR test mode.
(Active-High).
Enables the test mode control register for shifting in selected
tests by a serial port (EXDNUP). Serial stream setup is 18 bits long.
(Active-High).
Enables external manual test control of 622.08 MHz clock
phase selection through ETOGGLE and EXDNUP inputs.
(Active +pulse).
Moves 622.08 MHz clock selection one phase per positive
pulse >50 ns.
Direction of phase change: 0 = down; 1 = up.
(Active-High).
Controls bypass of 16 PLL-generated phases with 16 low-
speed phases, generated by test logic.
Test mode output port. Can monitor recovered channel 77.76 Mbytes/s data
byte and clock. Selection under control of test mode register.
ECSEL
I
ETOGGLE
I
EXDNUP
TSTPHASE
I
I
TSTMUX[8:0]
O
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