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參數(shù)資料
| 型號(hào)： | CDRH3D16 |
| 廠商： | Monolithic Power Systems, Inc. |
| 英文描述： | 1.6MHz Synchronous Step-Down plus 200mA LDO |
| 中文描述： | 1.6MHz的同步降壓型加200mA的LDO穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 475K |
| 代理商： | CDRH3D16 |
MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO
MP2101 Rev. 1.0
8/18/2006
www.MonolithicPower.com
10
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
2006 MPS. All Rights Reserved.
TM
Switcher Input Capacitor Selection
The input capacitor (C
IN1
) reduces the surge
current drawn from the input and switching
noise from the device. The input capacitor
impedance at the switching frequency should
be less than the input source impedance to
prevent high frequency switching current
passing to the input. Ceramic capacitors with
X5R
or
X7R
dielectrics
recommended because of their low ESR and
small temperature coefficients. For most
applications, a 4.7μF capacitor is sufficient.
are
highly
Switcher Output Capacitor Selection
The output capacitor (C
O1
) keeps the output
voltage ripple small and ensures regulation loop
stability. The output capacitor impedance
should be low at the switching frequency.
Ceramic capacitors with X5R or X7R dielectrics
are recommended. The output ripple
V
OUT
is
approximately:
(
×
)
×
×
+
×
×
×
≤
1
O
OSC
OSC
1
IN
1
1
OUT
L
1
IN
f
1
OUT
V
1
OUT
V
C
f
8
ESR
V
V
V
Thermal Dissipation
Power dissipation should be considered when
both channels of the MP2101 provide maximum
output current at high ambient temperatures. If
the junction temperature rises above 150
°
C, the
two channels will shut down.
The junction-to-ambient thermal resistance of
the 10-pin QFN (3mm x 3mm) R
Θ
JA
is 50
°
C/W.
The maximum power dissipation is about 1.6W
when the MP2101 is operating in a 70
°
C
ambient temperature environment.
W
6
W
/
C
50
C
70
C
o
150
PD
o
o
MAX
=
=
Start-Up Consideration
To ensure a smooth start-up of OUT1 and
OUT2, it is recommended that the enable
signals (EN1 and EN2) be asserted only after
the input power rails have been stabilized. If
EN1 and EN2 are tied to input rails directly, the
UVLO of the MP2101 will dictate when the part
starts switching. Since for certain systems, the
input
supply
may
have
impedance
during
ramp
depending solely on UVLO to start the part may
cause input rail dip and output bounce. If the
system designer can not provide the enable
signal after input power rail is fully established,
it is recommended that EN1 and EN2 are
connected to the input power rail through a RC
delay network (as shown in Figure 2). The RC
time constant needs to be significantly large
compare to the ramp-up time of the input power
rail, which is usually of a few ms.
relatively
up,
high
therefore
PC Board Layout
The high current paths (GND, IN1/IN2 and
SW1) should be placed very close to the device
with short, direct and wide traces. Input
capacitors should be placed as close as
possible to the respective IN and GND pins.
The external feedback resistors should be
placed next to the FB pins. Keep the switching
nodes SW1 short and away from the feedback
network.
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