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參數(shù)資料
| 型號(hào)： | CDP68HC68W1 |
| 廠商： | Intersil Corporation |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 139K |
| 代理商： | CDP68HC68W1 |
10
V
SYS
This input is connected to the system voltage. After the CPU
initiates power down by setting bit 6 in the Interrupt Control
Register to “1”, the level on this pin will terminate power
down if it rises about 0.7V above the level at the V
BATT
input
pin after previously falling below V
BATT
+0.7V. When power
down is terminated, the PSE pin will return high and the
Clock Output will be enabled. The CPUR output pin will also
return high. The logic level present at this pin at the end of
POR determines the CDP68HC68T1’s operating mode.
V
BATT
The oscillator power source. The positive terminal of the bat-
tery should be connected to this pin. When the level on the
V
SYS
pin falls below V
BATT
+0.7V, the V
BATT
pin will be
internally connected to the V
DD
pin. When the voltage on
V
SYS
rises a threshold above (0.7V) the voltage on V
BATT
,
the connection from V
BATT
to the V
DD
pin is opened. When
the “LINE” input is used as the frequency source, V
BATT
may
be tied to V
DD
or V
SS
. The “XTAL IN” pin must be at V
SS
if
V
BATT
is at V
SS
. If V
BATT
is connected to V
DD
, the “XTAL
IN” pin can be tied to V
SS
or V
DD
.
XTAL IN, XTAL OUT
These pins are connected to a 32,768Hz. 1.048576MHz,
2.097152MHz or 4.194304MHz crystal. If an external clock
is used, it should be connected to “XTAL IN” with ‘XTAL
OUT” left open.
V
DD
The positive power-supply pin.
Clock Control Register
START-STOP
A high written into this bit will enable the counter stages of
the clock circuitry. A low will hold all bits reset in the divider
chain from 32Hz to 1Hz. A clock out selected by bits 0, 1 and
2 will not be affected by the stop function except the 1Hz and
2Hz outputs.
LlNE-XTAL
When this bit is set high, clock operation will use the 50 or
60-cycle input present at the LINE input pin. When the bit is
low, the crystal input will generate the 1Hz time update.
XTAL Select
One of 4 possible crystals is selected by value in these two
bits:
0 = 4.194304MHz
1 = 2.097152MHz
2 = 1.048576MHz
3 = 32,768Hz
50-60Hz
50Hz is selected as the line input frequency when this bit is
set high. A low will select 60Hz. The power-sense bit in the
Interrupt Control Register must be set low for line frequency
operation.
Clock Out
The three bits specify one of the 7 frequencies to be used as
the squarewave clock output:
0 = XTAL
1 = XTAL/2
2 = XTAL/4
3 = XTAL/8
4 = Disable (low output)
5 = 1Hz
6 = 2Hz
7 = 50Hz or 60Hz
XTAL Operation = 64Hz
All bits are reset by a power-on reset. Therefore, the XTAL is
selected as the clock output at this time.
Interrupt Control Register
Watchdog
When this bit is set high, the watchdog operation will be
enabled. This function requires the CPU to toggle the CE pin
periodically without a serial-transfer requirement. In the
event this does not occur, a CPU reset will be issued. Status
Register must be read before re-enabling watchdog.
Power Down
A high in this location will initiate a power down. A CPU reset
will occur, the CLK OUT and PSE output pins will be set low
and the serial interface will be disabled.
XTAL
IN
22M
T1
XTAL
OUT
R
C
C2
10 - 40pF
C1
5 - 30pF
NOTES:
7. All frequencies recommended oscillator circuit. C1, C2 values
crystal dependent.
8. R used for 32KHz operation only. 100K - 300K range as specified
by crystal manufacturer.
FIGURE 7. OSCILLATOR CIRCUIT
CLOCK CONTROL REGISTER (Write/Read) - Address 31H
D7
D6
D5
D4
D3
D2
D1
D0
START
LINE
XTAL
XTAL
50Hz
CLK OUT
CLK OUT
CLK OUT
SEL
SEL
STOP
XTAL
1
0
60Hz
2
1
0
CDP68HC68T1
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