參數(shù)資料
型號(hào)： CDP68HC68S1M
廠商： HARRIS SEMICONDUCTOR
元件分類： 微控制器/微處理器
英文描述： Serial Multiplexed Bus Interface
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 139K
代理商： CDP68HC68S1M
8
Power Sensing (See Figure 3)
When Power Sensing is enabled (Bit 5 = 1 in Interrupt Con-
trol Register), AC transitions are sensed at the LINE input pin.
Threshold detectors determine when transitions cease. After
a delay of 2.68ms to 4.64ms, plus the external input circuit RC
time constant, an interrupt is generated and a bit is set in the
Status Register. This bit can then be sampled to see if system
power has turned back on. See PIN FUNCTIONS, LINE PIN.
The power-sense circuitry operates by sensing the level of the
voltage presented at the line input pin. This voltage is cen-
tered around V
DD
and as long as it is either plus or minus a
threshold (about 1V) from V
DD
a power-sense failure will not
be indicated. With an AC signal present, remaining in this
V
DD
window longer than a minimum of 2.68ms will activate
the power-sense circuit. The larger the amplitude of the AC
signal, the less time it spends in the V
DD
window, and the less
likely a power failure will be detected. A 60Hz, 10V
P-P
sine-
wave voltage is an applicable signal to present at the LINE
input pin to setup the power sense function.
Power Down (See Figure 4)
Power down is a processor-directed operation. A bit is set in
the Interrupt Control Register to initiate operation. 3 pins are
affected. The PSE (Power Supply Enable) output, normally
high, is placed low. The CLK OUT is placed low. The CPUR
output, connected to the processors reset input is also
placed low. In addition, the Serial Interface is disabled.
Power Up (See Figure 5 and Figure 6)
Two conditions will terminate the Power-Down mode. The
first condition (See Figure 5) requires an interrupt. The inter-
rupt can be generated by the alarm circuit, the programma-
ble periodic interrupt signal, or the power sense circuit.
The second condition that releases Power Down occurs
when the level on the V
SYS
pin rises about 0.7V above the
level at the V
BATT
input, after previously falling to the level of
V
BATT
(See Figure 6) in the Battery Backup Mode or V
SYS
falls to logic low and returns high in the Single Supply Mode.
FIGURE 3. POWER-SENSING FUNCTIONAL DIAGRAM
FIGURE 4. POWER-DOWN FUNCTIONAL DIAGRAM
FIGURE 5. POWER-UP FUNCTIONAL DIAGRAM (INITIATED
BY INTERRUPT SIGNAL
XTAL IN
XTAL OUT
LINE
V
DD
REAL-TIME CLOCK
CDP68HC68T1
STATUS REGISTER
INT
INT
CPU
CDP68HC05C16B
V
DD
0V
I
V
SYS
INTERRUPT
CONTROL
REGISTER
I
SERIAL
INTERFACE
CLK
OUT
CPUR
REAL-TIME CLOCK
CDP68HC68T1
PSE
OSC
RESET
CPU
CDP68HC05C4B
MISO
MOSI
FROM SYSTEM
POWER
TO SYSTEM
POWER CONTROL
POWER
SENSE
OR
ALARM
CIRCUIT
SERIAL
INTERFACE
PERIODIC
INTERRUPT
SIGNAL
POWER
UP
REAL-TIME CLOCK
CDP68HC68T1
PSE
CPUR
CLK
OUT
INT
MISO
MOSI
CDP68HC68T1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDP68HC68T WAF 制造商:Harris Corporation 功能描述:
CDP68HC68T1 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control
CDP68HC68T1_06 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control
CDP68HC68T1_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control
CDP68HC68T1D 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control
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