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參數(shù)資料
| 型號(hào)： | CDP68HC68S1M |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Serial Multiplexed Bus Interface |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 139K |
| 代理商： | CDP68HC68S1M |
14
Read/Write Data (See Figure 10)
Read/Write data follows the Address/Control byte.
Watchdog Reset - (See Figure 11)
When watchdog operation is selected, CE must be toggled
periodically or a CPU reset will be outputted.
Address And Data
Data transfers can occur one byte at a time (Figure 12) or in
a multibyte burst mode (Figure 13). After the Real-Time
Clock enabled, an Address/Control word is sent to set the
CLOCK or RAM and select the type of operation (i.e., Read
or Write). For a single-byte Read or Write, one byte is trans-
ferred to or from the Clock Register or RAM location speci-
fied in the Address/Control byte and the Real-Time Clock is
then disabled. Write cycle causes the latched Clock Register
or RAM address to automatically increment. Incrementing
continues after each transfer until the device is disabled.
After incrementing to 1FH the address will “wrap” to 00H and
continue. Therefore, when the RAM is selected the address
will “wrap” to 00H and when the clock is selected the
address will “wrap” 20H.
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
BIT
D2
D1
D0
D3
D4
D5
D6
D7
D2
D1
D0
D3
D4
D5
D6
D7
CE
SCK (NOTE)
MOSI
MISO
NOTE: SCK can be either polarity.
FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS
CE
SERVICE
TIME
SERVICE
TIME
SCK
CPUR
FIGURE 11. WATCHDOG OPERATION WAVEFORMS
CDP68HC68T1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CDP68HC68T WAF | 制造商:Harris Corporation 功能描述: |
| CDP68HC68T1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
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| CDP68HC68T1_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
| CDP68HC68T1D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
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