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參數(shù)資料
| 型號(hào)： | CDP68HC68P1E |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Serial 8-Bit Input/Output Port |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDIP16 |
| 封裝： | PLASTIC, MS-001BB, DIP-16 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 139K |
| 代理商： | CDP68HC68P1E |
7
Functional Description
The SPI real-time clock consists of a clock/calendar and a
32 x 8 RAM. Communications is established via the SPI
(Serial Peripheral Interface) bus. In addition to the clock/cal-
endar data from seconds to years, and system flexibility pro-
vided by the 32-byte RAM, the clock features computer
handshaking with an interrupt output and a separate square-
wave clock output that can be one of 7 different frequencies.
An alarm circuit is available that compares the alarm latches
with the seconds, minutes and hours time counters and acti-
vates the interrupt output when they are equal. The clock is
specifically designed to aid in power-down/up applications
and offers several pins to aid the designer of battery backup
systems.
Mode Select
The voltage level that is present at the V
SYS
input pin at the
end of power-on-reset selects the device to be in the single
supply or battery backup mode.
Single-Supply Mode
If V
SYS
is a logic high when power-on-reset is completed,
CLK OUT, PSE and CPUR will be enabled and the device
will be completely operational. CPUR will be placed low if the
logic level at the V
SYS
pin goes low. If the output signals
CLK OUT, PSE and CPUR are disabled due to a power-
down instruction, V
SYS
brought to a logic low and then to a
logic high will re-enable these outputs. An example of the
single-supply mode is where only one supply is available
and V
DD
, V
BATT
and V
SYS
are tied together to the supply.
Battery Backup Mode
If V
SYS
is a logic low at the end of power-on-reset, CLK
OUT, PSE and CPUR will be disabled (CLK OUT, PSE and
CPUR low). This condition will be held until V
SYS
rises to a
threshold (about 0.7V) above V
BATT
. The outputs CLK OUT,
PSE and CPUR will then be enabled and the device will be
operational. If V
SYS
falls below a threshold above V
BATT
the
outputs CLK OUT, PSE and CPUR will be disabled. An
example of battery backup operation occurs if V
SYS
is tied to
V
DD
and V
DD
is not connected to a supply when a battery is
connected to the V
BATT
pin. (See Pin Functions, V
BATT
for
Battery Backup Operation.)
Clock/Calendar (See Figure 1 and Figure 2)
The clock/calendar portion of this device consists of a long
string of counters that is toggled by a 1Hz input. The 1Hz
input is generated by a prescaler driven by an on-board
oscillator that utilizes one of four possible external crystals or
that can be driven by an external clock source. The 1Hz trig-
ger to the counters can also be supplied by a 50Hz or 60Hz
input source that is connected to the LINE input pin.
The time counters offer seconds, minutes and hours data in
12 hour or 24 hour format. An AM/PM indicator is available
that once set, toggles every 12 hours. The calendar counters
consist of day (day of week), date (day of month), month and
years information. Data in the counters is in BCD format.
The hours counter utilizes BCD for hour data plus bits for
12/24 hour and AM/PM. The 7 time counters are accessed
serially at addresses 20H through 26H. (See Table 1).
RAM
The real-time clock also has a static 32 x 8 RAM that is
located at addresses 00-1FH. Transmitting the address/con-
trol word with bit-5 low selects RAM access. Bits 0 through 4
select the RAM location.
Alarm
The alarm is set by accessing the three alarm latches and
loading the required data. The alarm latches consist of sec-
onds, minutes and hours registers. When their outputs equal
the values in the seconds, minutes and hours time counters,
an interrupt is generated. The interrupt output will go low if
the alarm bit in the Interrupt Control Register is set high. The
alarm interrupt bit in the Status Register is set when the
interrupt occurs (see Pin Functions, INT Pin). To preclude a
false interrupt when loading the time counters, the alarm
interrupt bit should be set low in the Interrupt Control Regis-
ter. This procedure is not required when the alarm time is
set.
Watchdog Function (See Figure 6)
When bit 7 in the Interrupt Control Register is set high, the
Clock’s CE (chip enable) pin must be toggled at a regular
interval without a serial data transfer. If the CE is not toggled,
the clock will supply a CPU reset pulse and bit 6 in the Sta-
tus Register will be set. Typical service and reset times are
listed below.
Clock Out
The value in the 3 least significant bits of the Clock Control
Register selects one of seven possible output frequencies.
(See Clock Control Register). This squarewave signal is
available at the CLK OUT pin. When Power-Down operation
is initiated, the output is set low.
Control Registers and Status Registers
The operation of the Real-Time Clock is controlled by the
Clock Control and Interrupt Control Registers. Both registers
are Read-Write Registers. Another register, the Status Reg-
ister, is available to indicate the operating conditions. The
Status Register is a Read only Register.
Power Control
Power control is composed of two operations, Power Sense
and Power Down/Up. Two pins are involved in power sens-
ing, the LINE input pin and the INT output pin. Two additional
pins are utilized during power-down/up operation. They are
the PSE (Power Supply Enable) output pin and V
SYS
input
pin.
50Hz
60Hz
XTAL
MIN
MAX
MIN
MAX
MIN
MAX
Service Time
-
10ms
-
8.3ms
-
7.8ms
Reset Time
20
40ms
16.7
33.3ms
15.6
31.3ms
CDP68HC68T1
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