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參數(shù)資料
| 型號： | CDP1878CE |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Dual Counter-Timer |
| 中文描述： | 2 TIMER(S), PROGRAMMABLE TIMER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 61K |
| 代理商： | CDP1878CE |
4-97
Mode 2
Operation of this mode is the same as mode 1, except the
outputs will change for one clock period only and then return
to the condition of TXO high and TXO low, and the counter is
reloaded
Mode 3
After the jam register is loaded with the required value, the
gate edge will initiate this mode. TXO will be set high, and
TXO will be set low. The clock will decrement the counter.
When zero is reached, TXO will go low and TXO will be high,
and the interrupt output will be set low. The counter is retrig-
gerable: While the counter is decrementing, a gate edge or
write to the control register with the jam-enable bit high, will
load the counter with the jam register value and restart the
one-shot operation.
MODE
CONTROL REGISTER
GATE CONTROL
2
Timeout Strobe
Selectable High or Low
Level Enables Operation
X X X X X 0 1 0
BUS 7
BUS 0
FIGURE 2. TIMEOUT STROBE (MODE 2) TIMING WAVEFORMS
NOTE: Write to control register with mode selects = 0
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
GATE
TXO
INT
1
2
3
3
LOAD COUNT = 3
0
1
2
3
0
1
2
3
3
0
1
2
3
SEE NOTE
MODE
CONTROL REGISTER
GATE CONTROL
3
Gate Controlled One-Shot
Selectable Positive or
Negative Going Edge
Initiates Operation
0 X X X X 0 1 1
BUS 7
BUS 0
FIGURE 3. GATE CONTROLLED ONE-SHOT (MODE 3) TIMING WAVEFORMS
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
GATE
TXO
INT
LOAD COUNT = 3
2
3
3
0
1
2
3
3
1
2
3
0
1
2
3
CDP1878C
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| CDP1879CD1 | CMOS Real-Time Clock |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1878D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CDP1878E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CDP1879 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Real-Time Clock |
| CDP1879C-1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Real-Time Clock |
| CDP1879C1D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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