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參數(shù)資料
| 型號： | CDP1878CD |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Dual Counter-Timer |
| 中文描述： | 2 TIMER(S), PROGRAMMABLE TIMER, CDIP28 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 61K |
| 代理商： | CDP1878CD |
4-98
Mode 4
A repetitive clock-wide output pulse will be output, with the
time between pulses equal to the counter’s value, (trailing
edge to leading edge). This model is software started with a
write to the control register if the gate level is valid. If the
counter is written to while decrementing, the new value will
not affect the counter’s operation until the present timeout
has concluded, unless the control register is written to with
the jam-enable bit high. If the gate input (TAG or TBG) is
used to start this mode, the first cycle following the gate
going true is indeterminate.
Mode 5
After the mode is initiated, the outputs will remain at one
level until the clock decrements the least significant byte of
the counter to N+1. The outputs will then change level and
the counter decrements the most significant byte to N+1.
The process will then repeat, resulting in a repetitive output
with a duty cycle directly controlled by the value in the
counter. The output period will be equal to LSB+MSB+2.
The interrupt output will become active after the MSB is
loaded into the counter and decrements to zero.
MODE
CONTROL REGISTER
GATE CONTROL
4
Rate Generator
Selectable High or Low
Level Enables Operation
X X X X X 1 0 0
BUS 7
BUS 0
FIGURE 4. RATE GENERATORS (MODE 4) TIMING WAVEFORMS
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
GATE
TXO
INT
LOAD COUNT = 3
N
3
0
1
N
3
0
2
3
0
1
2
3
0
1
2
3
1
2
3
MODE
CONTROL REGISTER
GATE CONTROL
5
Variable Duty Cycle
Selectable High or Low
Level Enables Operation
X X X X X 1 0 1
BUS 7
BUS 0
FIGURE 5. VARIABLE-DUTY CYCLE (MODE 5) TIMING WAVEFORMS
NOTE: In order to avoid unwanted starts when selecting mode 3 or 4, the gate signal must be set to the opposite level that will be pro-
grammed.
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
GATE
TXO
INT
LOAD COUNT LSB = 2 AND MSB = 1
LSB
LSB
MSB
1
0
1
1
0
2
0
1
1
2
0
1
0
1
2
0
1
2
CDP1878C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1878C | CMOS Dual Counter-Timer(CMOS 雙路計時器／定時器) |
| CDP1878CE | CMOS Dual Counter-Timer |
| CDP1879C-1 | CMOS Real-Time Clock |
| CDP1879CD1 | CMOS Real-Time Clock |
| CDP1879CD1X | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C SSOP-56 26/TUBE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1878CE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Dual Counter-Timer |
| CDP1878D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CDP1878E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CDP1879 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Real-Time Clock |
| CDP1879C-1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Real-Time Clock |
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