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參數(shù)資料
| 型號： | CDP1878CD |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Dual Counter-Timer |
| 中文描述： | 2 TIMER(S), PROGRAMMABLE TIMER, CDIP28 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 61K |
| 代理商： | CDP1878CD |
4-93
Functional Diagram
FUNCTIONAL DEFINITIONS FOR CDP1878C TERMINALS
TERMINAL
USAGE
TERMINAL
USAGE
V
DD
- V
SS
Power
TAO, TAO
Complemented outputs of Timer A
DB0-DB7
Data to and from device
TBO, TBO
Complemented outputs of Timer B
TPB/WR, RD
Directional Control Signals
TPA
Used with CDP1800-series processors, tied high
otherwise
A0, A1, A2
Addresses that select counters or registers
CS
Active high input that enables device
TACL, TBCL
Clocks used to decrement counters
INT
Low when counter is “0”
TAG, TBG
Gate inputs that control counters
RESET
When active, TAO, TBO are low, TAO, TBO are
high. Interrupt status register is cleared.
IO/MEM
Tied high in CDP1800 input/output mode, other-
wise tied low
RESET
RD
TPB/WR
IO/MEM
TPA
CS
A2
A1
A0
V
DD
V
SS
I-O
CONTROL
AND
LOGIC
DATA
BUS
DRIVERS
8-BIT
EXTERNAL
BUS
JAM
REGISTER A
HOLDING
REGISTER A
HOLDING
REGISTER B
JAM
REGISTER B
COUNTER A
COUNTER B
CONTROL REGISTER B
AND MODE CONTROL
INT AND
STATUS REGISTER
CONTROL REGISTER A
AND MODE CONTROL
INT
GATE A
TAO
TAO
CLOCK A
GATE B
TBO
TBO
CLOCK B
CDP1878C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1878C | CMOS Dual Counter-Timer(CMOS 雙路計時器／定時器) |
| CDP1878CE | CMOS Dual Counter-Timer |
| CDP1879C-1 | CMOS Real-Time Clock |
| CDP1879CD1 | CMOS Real-Time Clock |
| CDP1879CD1X | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C SSOP-56 26/TUBE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1878CE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Dual Counter-Timer |
| CDP1878D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CDP1878E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CDP1879 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Real-Time Clock |
| CDP1879C-1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Real-Time Clock |
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