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參數(shù)資料
| 型號(hào)： | CDP1877 |
| 廠商： | Intersil Corporation |
| 英文描述： | Programmable Interrupt Controller (PIC)(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（PIC）（可編程中斷控制器） |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 45K |
| 代理商： | CDP1877 |
4-85
PIC Programming Model
INTERNAL REGISTERS
The PIC has three write-only programmable registers and
two read-only registers.
Page Register
This write only register contains the high order vector
address the device will issue in response to an interrupt
request. This high-order address will be the same for any of
the 8 possible interrupt requests; thus, interrupt vectoring dif-
fers only in location within a specified page.
Control Register
The upper nibble of this write-only register contains the low
order vector address the device will issue in response to an
interrupt request. The lower nibble is used for a master
interrupt reset, master mask reset and for interval select.
Functional Definitions for CDP1877 and CDP1877C Terminals
TERMINAL
USAGE
TYPE
V
DD
- V
SS
Power
BUS0 - BUS7
Data Bus - Communicates Information to and from CPU
Bidirectional
IR0 - IR7
Interrupt Request Lines
Input
INTERRUPT
Interrupt to CPU
Output
MRD, MWR
Read/Write Controls from CPU
Input
TPA, TPB
Timing Pulses from CPU
Input
CS, CS
Chip Selects, Enable Chip if Valid during TPA
Input
CS/A
X
, CS/A
Y
Used as a Chip Select during TPA and as a Register Address During Read/Write Operations
Input
CASCADE
Used for Cascading Several PIC Units. The INTERRUPT Output from a Higher
Priority PIC can be Tied to this Input, or the Input can be Tied to V
DD
if Cascading is Not Used.
Input
BUS 7
BUS 0
PAGE REGISTER BITS
A12
WRITE ONLY
A15
A14
A13
A11
A10
A9
A8
BUS 7
BUS 0
CONTROL REGISTER BITS
B4
WRITE ONLY
B7
B6
B5
B3
B2
B1
B0
INTERVAL SELECT DETERMINES
NUMBER OF BYTES ALLOCATED TO
EACH INTERRUPT SERVICE ROUTINE
BIT 1
BIT 0
0
0
1
1
MASTER MASK RESET
0 RESETS ALL MASK REGISTER BITS
1 NO CHANGE
INTERVAL
2
4
8
16
0
1
0
1
MASTER INTERRUPT RESET
0 RESETS ALL INTERRUPT LATCHES, CLEARS ANY
PENDING INTERRUPTS
1 NO CHANGE
SETS UPPER BITS OF THE LOW ORDER VECTOR ADDRESS AS A
FUNCTION OF THE INTERVAL SELECT
CDP1877, CDP1877C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1877C | Programmable Interrupt Controller (PIC)(可編程中斷控制器) |
| CDP1877CE | Programmable Interrupt Controller (PIC) |
| CDP1877E | Programmable Interrupt Controller (PIC) |
| CDP1878CD | CMOS Dual Counter-Timer |
| CDP1878C | CMOS Dual Counter-Timer(CMOS 雙路計(jì)時(shí)器／定時(shí)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1877C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Interrupt Controller (PIC) |
| CDP1877CD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| CDP1877CE | 制造商:Harris Corporation 功能描述: |
| CDP1877CE WAF | 制造商:Harris Corporation 功能描述: |
| CDP1877D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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