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4-39
CDP1853, CDP1853C
FIGURE 5. N-BIT DECODER IN A ONE-LEVEL I/O SYSTEM
FIGURE 6. TWO-LEVEL I/O USING CDP1853 AND CDP1852
CS1
CS2
CDP1852
INPUT
PORT 1
MODE
7 INPUT PORTS
CLOCK
DATA
READ VIA
69 INSTRUCTION
STROBE
CS2
CS1
CDP1852
OUTPUT
PORT 1
MODE
7 OUTPUT PORTS
V
DD
SR
AVAILABLE
LOAD VIA 61
INSTRUCTION
TPB
CS1
CS2
CDP1852
INPUT
PORT 7
MODE
CLOCK
DATA
READ VIA
6F INSTRUCTION
STROBE
CS1
CS2
CDP1852
OUTPUT
PORT 7
MODE
V
DD
DATA
SR
DATA AVAILABLE
LOAD VIA 67
INSTRUCTION
TPB
CDP1800 SERIES
N0
MRD
TPB
V
DD
5 CDP1852 INPUT AND OUTPUT PORTS
N2
N2
N1
N1
N0
TPB
CLOCK B
CDP1853
0
TPA
CLOCK A
CE
2-6
1
7
CLOCK A
CLOCK B
CE
CDP1853
“62-6F”
INST
I/O
7 INPUT
6 OUTPUT
PORTS
CDP1852
CS2
CL CSI
DATA BUS
CDP1800 SERIES
TPA
BUS
MRD
TPB
NO, N1, N2
INTERCONNECTED
AS IN FIGURE 4
NO, N1, N2
CDP1853
DECODED
“61” INSTRUCTION
TPA
I
CLOCK A
CLOCK B
CE
CDP1853
“62-6F”
INST
I/O
7 INPUT
6 OUTPUT
PORTS
NO, N1, N2
CLOCK A
CLOCK B
CE
CDP1853
“62-6F”
INST
I/O
7 INPUT
6 OUTPUT
PORTS
NO, N1, N2
SECTIONS 3-7
NOTE: SYSTEM SHOWN WILL SELECT
UP TO 56 INPUT AND 48 OUTPUT
PORTS. WITH ADDITIONAL DECODING
AND OUTPUT PORTS CAN BE
FURTHER EXPANDED.
THE TOTAL NUMBER OF INPUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1853E | N-Bit 1 of 8 Decoder |
| CDP1854 | Programmable Universal Asynchronous Receiver/Transmitter (UART) |
| CDP1854AEX | Programmable Universal Asynchronous Receiver/Transmitter (UART) |
| CDP1854AC | Programmable Universal Asynchronous Receiver/Transmitter (UART) |
| CDP1854ACD | Programmable Universal Asynchronous Receiver/Transmitter (UART) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1853D3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1853D3R2540 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1853E | 制造商:RCA 功能描述: |
| CDP1854 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART) |
| CDP1854 DIE | 制造商:Harris Corporation 功能描述: |
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