參數(shù)資料
型號(hào): CDP1852CE
廠商: HARRIS SEMICONDUCTOR
元件分類: 微控制器/微處理器
英文描述: Byte-Wide Input/Output Port
中文描述: 8 I/O, PIA-GENERAL PURPOSE, PDIP24
文件頁(yè)數(shù): 6/7頁(yè)
文件大?。?/td> 218K
代理商: CDP1852CE
6
Dynamic Electrical Specification
Mode = 1 Output Port, See Figure 4, Input
tr, tf
15ns; C
L
= 50pF
PARAMETER
SYMBOL
V
DD
VOLTS
LIMITS (NOTE 1)
UNITS
-
55
o
C, +25
o
C
+125
o
C
(NOTE 1)
MIN
MAX
(NOTE 1)
MIN
MAX
Clock Pulse Width
t
CLK
5
170
-
260
-
ns
10
90
-
130
-
ns
Write Width Duration
t
WW
5
200
-
260
-
ns
10
110
-
130
-
ns
Clear Pulse Width
t
CLR
5
110
-
135
-
ns
10
60
-
75
-
ns
Data-In to Clock Fall Setup Time
t
DS
5
-10
-
-10
-
ns
10
-5
-
-5
-
ns
Data Hold from Write Termination
t
DH
5
130
-
170
-
ns
10
70
-
90
-
ns
Select-After Clock-Fall Hold Time
t
SH
5
0
-
0
-
ns
10
0
-
0
-
ns
Propagation Delay Times:
Clear to Data
t
RDO
5
-
215
-
290
ns
10
-
140
-
190
ns
Write to Data Out
t
WDO
5
-
250
-
350
ns
10
-
130
-
190
ns
Data In to Data Out
t
DDO
5
-
150
-
200
ns
10
-
80
-
100
ns
Clear to SR
t
RSR
5
-
175
-
240
ns
10
-
120
-
160
ns
Clock to SR
t
CSR
5
-
170
-
240
ns
10
-
90
-
120
ns
Deselect to SR
t
SSR
5
-
170
-
240
ns
10
-
90
-
120
ns
NOTE:
1. Time required by a device to allow for the indicated function.
CDP1852/3, CDP1852C/3
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