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參數(shù)資料
| 型號： | CDP1852C |
| 廠商： | Intersil Corporation |
| 英文描述： | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| 中文描述： | 同時，8位，模式親可編程輸入/輸出端口。（并行8位可編程模式的I / O端口） |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 63K |
| 代理商： | CDP1852C |
4-26
FIGURE 6. MODE 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
FIGURE 7. OUTPUT PORT MODE 1 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION
SERVICE REQUEST TRUTH TABLE
CS1
or
CS2
CLOCK
or
CLEAR
SR/SR
1
SR/SR
0
DATA OUT
CLEAR
CS1
CS2
(NOTE 1)
MODE 1 TRUTH TABLE
CLOCK
CS1-CS2
CLEAR
DATA OUT EQUALS
0
X
0
0
0
X
1
Data Latch
X
0
1
Data Latch
1
1
X
Data In
CS1
CS2 : CS1 = 0, CS2 = 1
NOTES
1. CS1
CS2 is the overlap of CS1
=
0 and CS2 = 1.
2. Write is the overlap of CS1
CS2 and CLOCK.
SR
DATA IN
CLOCK
t
WW
t
SH
t
CLK
t
CSR
t
SSR
t
WDO
t
DS
t
RDO
t
RSR
t
CLR
t
DH
t
DDO
(NOTE 2)
CS2
CDP1852
DATA BUS
CS1
CLOCK
MODE
DATA IN
SR
DATA
OUT
DATA OUT TO
PERIPHERAL DEVICE
SIGNAL THAT INDICATES
DATA IS READY
V
DD
CDP1802
MRD
TPB
N
X
MEMORY
ADDRESS
LINES
CDP1852 IS SELECTED
AND DATA IS
STROBED INTO IT’S
REGISTER WITH TPB
N
X
DATA IS OUTPUTTED
FROM THE CDP1852
AND THE PERIPHERAL
DEVICE IS SIGNALED
TPB
MRD
DATA BUS
DATA TO
SR/SR
VALID
DATA
PERIPHERAL
DEVICE
CDP1852, CDP1852C
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PDF描述 |
|---|---|
| CDP1853C | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853CD3 | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853 | N-Bit 1 of 8 Decoder |
| CDP1853CD | N-Bit 1 of 8 Decoder |
| CDP1853CDX | N-Bit 1 of 8 Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1852C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP1852CD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1852CD3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1852CE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1852D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Byte-Wide Input/Output Port |
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