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參數(shù)資料
| 型號： | CDP1852C |
| 廠商： | Intersil Corporation |
| 英文描述： | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| 中文描述： | 同時，8位，模式親可編程輸入/輸出端口。（并行8位可編程模式的I / O端口） |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 63K |
| 代理商： | CDP1852C |
4-23
Input Port Mode 0 - Typical Operation
General Operation
When the mode control is tied to V
SS
, the CDP1852
becomes an input port. In this mode, the peripheral device
places data into the CDP1852 with a strobe pulse and the
CDP1852 signals the microprocessor that data is ready to
be transferred on the strobe’s trailing edge via the SR output
line. The CDP1802 then issues an input instruction that
enables the CDP1852 to place the information from the
peripheral device on the data bus to be entered into a mem-
ory location and the accumulator of the microprocessor.
Detailed Operation
(See Figure 5)
The STROBE from the peripheral device places DATA into
the 8-bit register of the CDP1852 when it goes high and
latches the DATA on its trailing edge. The SR output is set
low on the strobe’s trailing edge. This output is connected to
a flag line of the CDP1802 microprocessor and software
polling will determine that the flag line has gone low and
peripheral data is ready to be transferred. The CDP1802
then issues an input instruction that places an N
X
line high.
With the MRD line also high, the CDP1852 is selected and
its output drivers place the DATA from the peripheral device
on the DATA BUS. When the CDP1802 selected the
CDP1852, it also selected and addressed the memory via
one of the 16 internal address registers selected by an
internal “X” register. The data from the CDP1852 is therefore
entered into the memory [Bus
→
M(R(X))]. The data is also
transferred to the D register (accumulator) in the
microprocessor (Bus
→
D). When the CDP1802’s execute
cycle is completed, the CDP1852 is deselected by the N
X
line returning low and its data output pins are three-stated.
The SR output returns high.
Minimum Data Setup Time
t
DS
5
-
-10
0
ns
10
-
-5
0
ns
Minimum Data Hold Time
t
DH
5
-
75
150
ns
10
-
35
75
ns
Data Out Hold Time (Note 2)
t
DOH
5
30
185
370
ns
10
15
100
200
ns
Propagation Delay Times, t
PLH
, t
PHL
Select to Data Out (Note 2)
t
SDO
5
30
185
370
ns
10
15
100
200
ns
Clear to SR
t
RSR
5
-
170
340
ns
10
-
85
170
ns
Clock to SR
t
CSR
5
-
110
220
ns
10
-
55
110
ns
Select to SR
t
SSR
5
-
120
240
ns
10
-
60
120
ns
NOTES:
1. Typical values are for T
A
= 25
o
C and nominal V
DD
.
2. Minimum value is measured from CS2, maximum value is measured from CS1/CS1.
Dynamic Electrical Specifications
At T
A
= -40
o
C to +85
o
C, V
DD
=
±
5%, t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF,
and 1 TTL Load
(Continued)
PARAMETER
V
DD
(V)
LIMITS
UNITS
MIN
(NOTE 1)
TYP
MAX
CDP1852, CDP1852C
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PDF描述 |
|---|---|
| CDP1853C | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853CD3 | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853 | N-Bit 1 of 8 Decoder |
| CDP1853CD | N-Bit 1 of 8 Decoder |
| CDP1853CDX | N-Bit 1 of 8 Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1852C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP1852CD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1852CD3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1852CE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1852D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Byte-Wide Input/Output Port |
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