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參數(shù)資料
| 型號： | CDP1826CE |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | CMOS 64-Word x 8-Bit Static RAM |
| 中文描述： | 64 X 8 STANDARD SRAM, 1000 ns, PDIP22 |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 42K |
| 代理商： | CDP1826CE |
6-53
Dynamic Electrical Specifications
At T
A
= -40 to +85
o
C, V
DD
= 5V
±
5%,Input t
R
, t
F
= 10ns; C
L
= 50pF and 1 TTL Load
PARAMETER
LIMITS
UNITS
CDP1826C
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
WRITE - CYCLE TIMES (FIGURES 6 AND 7)
Address to TPA Setup, High Byte
t
ASH
100
-
-
ns
Address to TPA Hold
t
AH
100
-
-
ns
Address Setup, Low Byte
T
ASL
500
250
-
ns
TPA Pulse Width
t
PAW
200
-
-
ns
Chip Select Setup
t
CS
700
350
-
ns
Write Pulse Width
t
WW
300
200
-
ns
Write Recovery
t
WR
100
-
-
ns
Data Setup
t
DS
400
200
-
ns
Data Hold from End of MWR
t
DH1
100
50
-
ns
Data Hold from End of Chip Select
t
DH2
125
50
-
ns
NOTES:
1. Time required by a limit device to allow tor the indicated function.
2. Typical values are for T
A
= 25
o
C and nominal V
DD
.
A0 - A5
HIGH ORDER
ADDRESS BYTE
LOW ORDER ADDRESS BYTE
t
AA
t
AC
t
RHZ
t
SHZ
VALID CHIP SELECT
HIGH IMPEDANCE
t
AM
MRD
CS1
CS2
BUS
VALID DATA
FIGURE 5. TIMING WAVEFORMS FOR READ-CYCLE 2 (TPA HIGH)
CDP1826C
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