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參數(shù)資料
| 型號(hào)： | CDP1826CE |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | CMOS 64-Word x 8-Bit Static RAM |
| 中文描述： | 64 X 8 STANDARD SRAM, 1000 ns, PDIP22 |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 42K |
| 代理商： | CDP1826CE |
6-52
Dynamic Electrical Specifications
At T
A
= -40 to +85
o
C, V
DD
= 5V
±
5%, Input t
R
, t
F
= 10ns; C
L
= 50pF and 1 TTL Load
PARAMETER
LIMITS
UNITS
CDP1826C
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
READ - CYCLE TIMES (FIGURES 4 AND 5)
Address to TPA Setup
t
ASH
100
-
-
ns
Address to TPA Hold
t
AH
100
-
-
ns
Access from Address Change
T
AA
-
500
1000
ns
TPA Pulse Width
t
PAW
200
-
-
ns
Output Valid from MRD
t
AM
-
500
1000
ns
Access from Chip Select
t
AC
-
500
1000
ns
CEO Delay from TPA
Edge
t
CA
-
150
300
ns
MRD to CEO Delay
t
MC
75
-
-
ns
Output High Z from Invalid MRD
t
RHZ
-
-
125
ns
Output High Z from Chip Deselect
t
SHZ
-
-
225
ns
NOTES:
1. Time required by a limit device to allow tor the indicated function.
2. Typical values are or T
A
= 25
o
C and nominal V
DD
.
A0 - A5
LOW ORDER ADDRESS BYTE
HIGH ORDER
ADDRESS BYTE
HIGH IMPEDANCE
t
AH
t
AA
TPA
t
PAW
t
AC
t
RHZ
t
SHZ
t
CA
t
MC
t
AM
VALID CHIP SELECT
VALID DATA
MRD
CS1 - CS2
CEO
BUS
t
ASH
FIGURE 4. TIMING WAVEFORMS FOR READ CYCLE 1
CDP1826C
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