參數(shù)資料
型號: CDP1826C
廠商: Intersil Corporation
英文描述: CMOS 64-Word x 8-Bit Static RAM
中文描述: 的CMOS 64字× 8位靜態(tài)存儲器
文件頁數(shù): 4/9頁
文件大?。?/td> 42K
代理商: CDP1826C
6-50
Signal Descriptions
A0 - A4, CS/A5 (Address Inputs):
These inputs must be
stable prior to a write operation, but may change asynchro-
nously during Read operations.
In an 1800 system, the multiplexed high-order address bit at
pin CS/A5 can be latched at the end of TPA. A high level will
provide a valid chip select for the CDP1826C. The low-order
address bit which appears after TPA is used for data word
selection. In non-1800 systems, TPA can be tied high to dis-
able the latch and allow the CS/A5 pin to function as a nor-
mal address input.
BUS 0 - BUS 7:
8-bit three-state common input/output data
bus.
TPA:
High-order address strobe input. The high-order
address bit at input CS/A5 is latched on the high-to-low tran-
sition of the TPA input. Tie TPA high to disable the CS/A5
latch feature.
CS1, CS2 (Chip Selector):
Either chip select (CS1 or CS2),
when not valid, powers down the chip, disables READ and
WRITE functions, and gates off the address and output buffers.
MRD, MWR:
Read and Write control signals. MWR over-
rides MRD, allowing the CDP1826C to be controlled from a
single R/W line.
CEO (Chip Enable Output):
Allows daisy chaining to addi-
tional memories. CEO is high whenever the CDP1826C is
selected. CEO is only active (low) for a Read cycle with the
CDP1826C deselected and the MRD input low.
V
DD
, V
SS
:
Power supply connections.
D
C
Q
A0
A1
A2
A3
A4
CS/A5
TPA
CS1
CS2
MWR
MRD
INPUT
ADDRESS
BUFFERS
XY
DECODE
BUS 0
BUS 2
BUS 1
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
64 x 8
MATRIX
INPUT/OUTPUT
DATA
BUFFERS
AND
CONTROL
FIGURE 2. FUNCTIONAL DIAGRAM
CEO
CDP1826C
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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