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參數(shù)資料
| 型號(hào)： | CDP1821CD3 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
| 中文描述： | 1K X 1 STANDARD SRAM, 255 ns, CDIP16 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 32K |
| 代理商： | CDP1821CD3 |
6-10
Data Retention Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
-55
o
C, +25
o
C
+125
o
C
UNITS
V
DR
(V)
V
DD
(V)
MIN
MAX
MIN
MAX
Minimum Data Retention Voltage
(Note 1)
V
DD
-
-
-
2
-
2.5
V
Data Retention Quiescent Current
(Note 1)
I
DD
2
-
-
50
-
200
μ
A
Chip Deselect to Data Retention Time
t
CDR
-
5
450
-
650
-
ns
Recovery to Normal Operation Time
t
RC
-
5
450
-
650
-
ns
NOTE:
1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing
FIGURE 3. LOW V
DD
DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
Burn-In Circuit
FIGURE 4. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM
V
DD
VDR
0.95 V
DD
0.95 V
DD
t
CDR
V
IH
V
IL
V
IH
V
IL
CS
t
F
t
R
t
RC
DATA RETENTION MODE
PACKAGE
V
DD
TEMPERATURE
DURATION
D
7V
+125
o
C
160 Hrs.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A11
A0
A1
A2
A3
A4
R
I
V
DD
/2
V
DD
O1
A9
A8
A7
A6
A5
A10
R
R
R
R
R
R
R
R
R
R
R
R
R
0
1.6
2.2
5.0
6.6
7.2
10.0
O1
A0
A1
0
V
DD
0
V
DD
V
DD
0
μ
s
A1 - A11 ARE DIVISION BY 2 BASED ON A0
R = 8.2k
20%
R
I
= 2k
20%
CDP1821C/3
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PDF描述 |
|---|---|
| CDP1822C | High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM |
| CDP1822C3 | High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM |
| CDP1822 | 256-Word x 4-Bit LSI Static RAM |
| CDP1822CD | 256-Word x 4-Bit LSI Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1821CD3R1783 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1821D | 制造商:Harris Corporation 功能描述: |
| CDP1822 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822 WAF | 制造商:Harris Corporation 功能描述: |
| CDP1822_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
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