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參數(shù)資料
| 型號(hào)： | CDP1821CD3 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
| 中文描述： | 1K X 1 STANDARD SRAM, 255 ns, CDIP16 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大小： | 32K |
| 代理商： | CDP1821CD3 |
6-9
Write Cycle Dynamic Electrical Specifications
t
R
, t
F
= 10ns, C
L
= 50pF
PARAMETER
SYMBOL
V
DD
(V)
-55
o
C, +25
o
C
+125
o
C
UNITS
MIN
MAX
MIN
MAX
Write Cycle Time
t
WC
5
300
-
420
-
ns
Address Setup Time (Note 1)
t
AS
5
60
-
84
-
ns
Address Hold Time (Note1)
t
AH
5
130
-
180
-
ns
Input Data Setup Time (Note 1)
t
DS
5
90
-
125
-
ns
Input Data Hold Time (Note 1)
t
DH
5
60
-
84
-
ns
Read/Write Pulse Width Low (Note 1)
t
WL
5
110
-
155
-
ns
NOTE:
1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
NOTES:
1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device.
2. Chip-Select (CS) permitted to change from low to high level or remain low.
3. Don’t care.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
CS
A0 - A9
R/W
(NOTE 3)
(NOTE 1)
t
WC
(NOTE 2)
(NOTE 3)
(NOTE 3)
DI
t
WL
t
AS
t
DS
t
DH
t
AH
CDP1821C/3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1822C | High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM |
| CDP1822C3 | High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM |
| CDP1822 | 256-Word x 4-Bit LSI Static RAM |
| CDP1822CD | 256-Word x 4-Bit LSI Static RAM |
| CDP1822CDX | 256-Word x 4-Bit LSI Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1821CD3R1783 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1821D | 制造商:Harris Corporation 功能描述: |
| CDP1822 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
| CDP1822 WAF | 制造商:Harris Corporation 功能描述: |
| CDP1822_1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256-Word x 4-Bit LSI Static RAM |
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