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參數(shù)資料
| 型號： | CDCU877ZQL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1.8V PHASE LOCK LOOP CLOCK DRIVER |
| 中文描述： | 1.8鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CDCU877ZQL |
SCAS688A JUNE 2003 REVISED JANUARY 2004
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
AVDD,
VDDQ
1.7 V
MIN
TYP
MAX
UNIT
VIK
Input (cl inputs)
II = 18 mA
1.2
V
VOH
High-level output voltage
IOH = 100
μ
A
1.7 V to
1.9 V
VDDQ
0.2
V
IOH = 9 mA
IOL = 100
μ
A
IOL = 9 mA
VO(DL) = 100 mV, OE = L
1.7 V
1.1
VOL
Low-level output voltage
0.1
V
1.7 V
0.6
IO(DL)
VOD
Low-level output current, disabled
1.7 V
100
μ
A
V
Differential output voltage (see Note 1)
1.7 V
0.5
CK, CK
1.9 V
±
250
II
Input current
OE, OS,
FBIN, FBIN
1.9 V
±
10
μ
A
IDD(LD)
Supply current, static (IDDQ + IADD)
CK and CK = L
1.9 V
500
μ
A
IDD
Supply current, dynamic (IDDQ
(see Note 2 for CPD calculation)
CK and CK = 270 MHz,
All outputs are open
(not connected to a PCB)
1.9 V
135
mA
ADD
All outputs are loaded with 2 pF and
120-
termination resistor
1.9 V
235
CI
Input capacitance
CK, CK
VI = VDD or GND
VI = VDD or GND
VI = VDD or GND
VI = VDD or GND
1.8 V
2
3
pF
FBIN, FBIN
1.8 V
2
3
CI
(
)
Change in input current
CK, CK
1.8 V
0.25
pF
FBIN, FBIN
1.8 V
0.25
NOTES:
1. VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition.
2. Total IDD = IDDQ + IADD = fCK
×
CPD
×
VDDQ, solving for CPD = (IDDQ + IADD)/(fCK
×
VDDQ) where fCK is the input frequency, VDDQ
is the power supply, and CPD is the power dissipation capacitance.
timing requirements over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
AVDD, VDD = 1.8 V
±
0.1 V
AVDD, VDD = 1.8 V
±
0.1 V
AVDD, VDD = 1.8 V
±
0.1 V
AVDD, VDD = 1.8 V
±
0.1 V
MIN
TYP
MAX
UNIT
fCK
fCK
tDC
tL
NOTES:
Clock frequency (operating, see Notes 1 and 2)
10
400
MHz
Clock frequency (application, see Notes 1 and 3)
160
340
MHz
Duty cycle, input clock
40%
60%
Stabilization time (see Note 4)
12
μ
s
1. The PLL must be able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other
timing parameters (used for low speed system debug).
3. Application clock frequency indicates a range over which the PLL must meet all timing parameters.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal
after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase
lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return
to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDCU877ZQLR | 功能描述:時鐘驅(qū)動器及分配 1.8v PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU877ZQLT | 功能描述:時鐘驅(qū)動器及分配 1.8v PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCUA877 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8-V PHASE LOCK LOOP CLOCK DRIVER |
| CDCUA877_1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8-V PHASE LOCK LOOP CLOCK DRIVER |
| CDCUA877ZQL | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8-V PHASE LOCK LOOP CLOCK DRIVER |
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