參數(shù)資料
型號: CDCU877ZQL
廠商: Texas Instruments, Inc.
英文描述: 1.8V PHASE LOCK LOOP CLOCK DRIVER
中文描述: 1.8鎖相環(huán)時鐘驅(qū)動器
文件頁數(shù): 5/17頁
文件大小: 410K
代理商: CDCU877ZQL
SCAS688A JUNE 2003 REVISED JANUARY 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
DDQ
or AV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Notes 1 and 2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
DDQ
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp voltage, I
OK
(V
O
< 0 or V
O
> V
DDQ
)
Continuous output current, I
O
(V
O
= 0 to V
DDQ
)
Continuous current through each V
DDQ
or GND
Storage temperature range, T
STG
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed
2. This value is limited to 2.5 V maximum.
0.5 V to 2.5 V
0.5 V to V
DDQ
+ 0.5 V
0.5 V to V
DDQ
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
±
50 mA
±
50 mA
±
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
°
C to 150
°
C
recommended operating conditions
MIN
NOM
MAX
UNIT
VDDQ
AVDD
VIL
VIH
IOH
IOL
VIX
VI
VID
Output supply voltage
1.7
1.8
1.9
V
Supply voltage
See Note 1
VDDQ
Low-level input voltage (see Note 2)
OE, OS
0.35
×
VDDQ
V
High-level input voltage (see Note 2)
CK, CK
0.65
×
VDDQ
V
High-level output current (see Figure 2)
9
mA
Low-level output current (see Figure 2)
9
mA
Input differential-pair cross voltage
(VDDQ/2)0.15
(VDDQ/2)+0.15
VDDQ+0.3
VDDQ+0.4
VDDQ+0.4
V
Input voltage level
(see Note 2 and Figure 9)
0.3
V
DC
0.3
V
Input differential voltage
AC
0.6
V
°
C
TA
NOTES:
Operating free-air temperature
40
85
1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the
recommended operating conditions and no timing parameters are ensured.
2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK
and CK VIH and VIL limits define the dc low and high levels for the logic detect state.
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