參數(shù)資料
型號： CDCE401YS
廠商： Texas Instruments, Inc.
英文描述： OSCILLATOR IC WITH ELECTRONIC CALIBRATION
中文描述： 振蕩器IC與電子校準(zhǔn)
文件頁數(shù)： 4/19頁
文件大?。?/td> 246K
代理商： CDCE401YS
www.ti.com
DETAILED DESCRIPTION
CONTROL PIN EN: Enable
The functions of the EN control pin are listed and explained in
Table 2
.
SINGLE-PIN INTERFACE CONTROL COMMANDS
The CDCE401 can be configured and programmed via the SDATA input pin. For this purpose, a
pulse-code-shaped signal must be applied to the device as shown in the waveforms of
Figure 1
to select one of
the operation modes described in the
State Flow-Diagram of the Single-Pin Interface
section. During the
EEPROM programming phase, the device requires a stable VDD of 3.2 V ±100 mV for secure writing of the
EEPROM cells. After each
Write-to-WordX
, the written data is latched, made effective, and offers look-ahead
before the actual data is stored into the EEPROM.
T0130-01
VDD
Enter Programming
Sequence and Write
Word0 (Trim PPM)
EN/SDATA
Apply Application
VDD and Verify
Settings (Measure)
Perform
State Jump
Into
Program
EEPROM
Hold for Minimum
10 ms to Achieve
Safe Programming
Jump From
State 3
State 1
Back Into Normal
Application After
200- s Low
m
2.25 V
VDD
3.3 V
￡
￡
3.1 V
VDD
3.3 V
￡
￡
3.1 V
VDD
3.3 V
￡
￡
2.25 V
VDD
3.3 V
￡
￡
CDCE401
SCAS820–JUNE 2006
Table 2. EN Control Pin Functions
EN
0
1
FUNCTION
Disabled: all current sources are switched off, output is in the high-impedance state.
Enabled: output follows the XIN/XOUT oscillation.
Table 3
summarizes all valid programming commands.
Figure 1. Typical Programming Cycle
Table 3. Single-Pin Interface Control Commands
SDATA
00 1100
FUNCTION
Enter
register programming mode
(state 1
→
state 2); bits must be sent in the specified order with the specified
timing. Otherwise, a time-out occurs.
Enter
register read-back mode
; bits must be sent in the specified order with the specified timing. Otherwise a
time-out occurs.
Write-to-word0
(state 2)
(1)(2)(3)
Write-to-word1
(state 2)
(1) (2) (3)
Write-to-word2
(state 2)
(1) (2) (3)
State-machine jump
: All other patterns not defined as follows cause
exit to normal mode.
Jump:
Exit write-to-RAM
(state 2
→
state 1)
Jump:
Enter EEPROM programming without an EEPROM lock
(state 2
→
state 3)
Jump:
Enter EEPROM programming with EEPROM lock
(state 2
→
state 4)
Jump:
Exit EEPROM programming
(state 3 or state 4
→
state 1)
11 1011
00 xxxx xxxx
10 xxxx xxxx
01 xxxx xxxx
11 xxxx xxxx
11 1111 1111
11 1111 0000
11 0101 0101
11 0000 0000
(1)
(2)
(3)
Each rising edge causes a bit to be latched.
Between the bits, some longer time delays can occur, but this has no effect on the data.
A
Write-to-WordX
is expected to be 10 bits long. After the 10
th
bit, the respective word is latched, and its effect can be observed as
look-ahead
function.
4
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