參數(shù)資料
型號: CDCE401
廠商: Texas Instruments, Inc.
英文描述: Oscillator IC with Electronic Calibration
中文描述: 具有電子校準(zhǔn)的振蕩器 IC
文件頁數(shù): 12/19頁
文件大?。?/td> 246K
代理商: CDCE401
www.ti.com
CDCE401
SCAS820–JUNE 2006
TIMING REQUIREMENTS (continued)
over recommended ranges of supply voltage, load, and operating free-air temperature
PARAMETER
MIN
NOM
MAX
UNIT
OG0 = 1
OG0 = 1
OG0 = 0
OG0 = 0
OG1 = 1
OG1 = 0
OG1 = 1
OG1 = 0
CXx7
CXx6
CXx5
CXx4
CXx3
CXx2
CXx1
CXx0
25
17
16
11
Base input capacitance into XOUT,
measured single-ended with all CXx turned
off
C
BASE_XOUT
pF
6
3
pF
1.5
0.75
375
187
94
47
Crystal tune capacitance, measured single-ended against
VSS (subtracted from C
), i.e.:
CXI[0:7] = C
XIN
– C
(OGx) or
CXO[0:7] = C
XOUT
– C
BASE
(OGx)
CXI[7:0]
CXO[7:0]
fF
FOUT OUTPUT PARAMETER
f
CLK_OUT
Crystal frequency
t
r
/t
f
Rise and fall time
20
100
MHz
ns
10% to 90% VDD and
C
Load,max
= 15 pF
C
Load,max
= 15 pF
2
3
f
max
C
Load
Highest output frequency
Load capacitance
100
15
55%
MHz
pF
At VDD/2, 20 MHz
freq
80
MHz
At VDD/2, 80 MHz < freq
100MHz
45%
50%
odc
Output duty cycle
40%
50%
60%
SDATA/EN TIMING
f
SDATACLK
t
1
Repeat frequency of programming
LOW signal: high-pulse duration
LOW signal: low-pulse duration while entering programming sequence
LOW signal: low-pulse duration while programming bits
HIGH signal: high-pulse duration
HIGH signal: low-pulse duration while entering programming sequence
HIGH signal: low-pulse duration while programming bits
Time delay between SDATA signal and SDATA_Delayed signal at VDD = 3.3 V
Time between bits during
enter programming mode
and
enter read-back mode
beyond which a time-out must occur
EN high time before first SDATA can be clocked in
EN low time before first SDATA bit is clocked in
Rise and fall time from 20% to 80% of VDD
200
kHz
μ
s
0.5
3.8
3.8
3.8
0.5
0.5
1.5
10
1
4
1.2
4.2
t
2
μ
s
t
3
4
1
4.5
1.2
μ
s
t
4
μ
s
t
5
t
6
2.5
3.5
30
μ
s
μ
s
t
7
t
8
t
r
/t
f
60
μ
s
μ
s
ns
2
1
10
15
12
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