參數(shù)資料
型號(hào): CDCD5704_07
廠商: Texas Instruments, Inc.
英文描述: Rambus XDR CLOCK GENERATOR
中文描述: Rambus公司的XDR時(shí)鐘發(fā)生器
文件頁數(shù): 10/19頁
文件大小: 260K
代理商: CDCD5704_07
www.ti.com
CDCD5704
SCAS823–DECEMBER 2006
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
6.8
45
TYP
MAX
7.2
UNIT
I
OL
/I
REF
I
OL,ABS
Ratio of output low current to reference current
Minimum current at V
OL,ABS(5)
7
V
OL,ABS
= 0.85 V
V
DD
= 2.375 V to 2.625 V,
I
OH
= 4 mA
V
DD
= 2.375 V to 2.625 V,
V
O
= 0.8 V
CLK0 to CLK4
V
I
= 0 V or V
DD
V
I
= 0 V or V
DD
mA
V
OL,SDA
SDA output low voltage
0.4
V
I
OL,SDA
SDA output low current
6
mA
I
OZ
I
IR
I
IL
AC DEVICE CHARACTERISTICS
Input capacitance, REFCLK,
C
IR
REFCLKB
(6)
C
IL
Input capacitance logic pins
(7)
Output 3-state current
REFCLK input current
Logic input current
±
50
±
5
±
10
μ
A
μ
A
μ
A
2
7
pF
2
10
pF
300 MHz to 667 MHz, possible
SSC is not taken into account
10,000 cycles, 300 MHz
to 635 MHz
(9)
10,000 cycles, 636 MHz
to 667 MHz
(9)
300-MHz–667-MHz output
(10)
300-MHz–667-MHz output
(10)
V
= 2.375 V to 2.625 V,
T = 0 to 70
°
C
t
CYCLE
Clock cycle time
(8)
1.5
3.33
ns
40
t
jit(per)
|Cycle-to-cycle jitter| of 1–6 clock cycles
ps
30
L
1
L
20
SSB phase noise at 1 MHz
SSB phase noise at 20 MHz
–115
–150
–97
–128
dBc/Hz
dBc/Hz
t
skew(o)
Drift in t
skew(o)(11)
15
ps
odc
Output duty cycle
45%
50%
55%
40
30
100
300
300 MHz to 635 MHz
636 MHz to 667 MHz
t
ODC,ERR
|Cycle-to-cycle| duty-cycle error
ps
t
ERR,SSC
t
r
/t
f
PLL output phase error when tracking SSC
Output rise and fall time
–100
100
ps
ps
V
OUT
= 20%–80%
V
= 20%–80%, f
out
= 300 MHz
to 667 MHz
V
OL
= 0.9 V
Time from VDD, VDDP, VDDC
being applied and settled until
clock outputs are settled
Time from signals for selecting a
mode of operation (1) or (2)
applied and settled until clock
outputs are settled
t
cr
/t
cf
Difference between output rise and fall times
100
ps
Z
OUT
Output dynamic impedance
(12)
750
t
L
Power-up lock time
3
ms
PLL lock time after (1) frequency change via
serial interface (programming of SCL and SDA
pins completed) or (2) EN and/or BYPASS
changed state
t
L(
ω
)
3
ms
(5)
(6)
(7)
(8)
Minimum I
is measured at the clock output pins of the package, as shown in
Figure 3
.
Capacitance measured at frequency = 1 MHz, dc bias = 0.9 V, and V
AC
< 100 mV
Capacitance measured at frequency = 1 MHz, dc bias = 0.9 V, and V
< 100 mV
Maximum and minimum output clock cycle times are based on nominal output frequency of 300 MHz and 667 MHz, respectively. For
spread-spectrum-modulated differential or single-ended REFCLK, the output clock tracks the modulation of the input.
Output short-term jitter specification is the absolute value of the worst-case deviation and is defined in the
Jitter
section.
(10) Device must not exceed the upper limit of L(f) for 1-MHz to 100-MHz offset as shown in the
Phase Noise
section.
(11) t
is the timing difference between any two of the four differential clocks and is measured at common-mode voltage.
t
skew
is the
change in t
when the operating temperature and supply voltage change.
(12) Z
is defined at the output pins directly. The value is determined as the ac small-signal impedance at low frequencies (< 100 kHz)
and when output is driving a high state.
(9)
10
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