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參數(shù)資料
| 型號： | CDC9449 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC時鐘合成器/驅動器(SDRAM 時鐘支持)) |
| 中文描述： | 電腦主板時鐘Sythesizer /支持與SDRAM時鐘驅動器（電腦時鐘合成器/驅動器（SDRAM的時鐘支持）） |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 115K |
| 代理商： | CDC9449 |
CDC9449
PC CLOCK SYNTHESIZER/DRIVER
WITH SDRAM CLOCK SUPPORT
SCAS577 – AUGUST 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
ms
Stabilization time
After power up
3
After change to SEL(0:1)
3
ms
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at XIN.
switching characteristics (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
Jitter
Duty cycle
tr§
tf§
SBCLKn, FCCLK, AUDIO, 1/2 AUDIO
±
500
ps
SBCLKn, FCCLK, AUDIO, 1/2 AUDIO
45%
55%
Any output
0.5
2
ns
Any output
0.5
2
ns
Specifications are applicable only after the PLL stabilization time has elapsed.
§Rise and fall times are characterized using the test circuit shown in Figure 1.
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
tr
tf
2.4 V
1.5 V
0.4 V
3.3-V CLOCK WAVEFORMS
tc
tw
NOTES: A. CL includes probe and jig capacitance.
CL = 20 pF (SBCLKn, FCCLK, AUDIO, 1/2 AUDIO, REF1, REF2)
CL = 45 pF (REF0)
B. The outputs are measured one at a time with one transition per measurement.
C. Duty cycle = (tw tc)
×
100%
Figure 1. Load Circuit and Voltage Waveforms
NOTES: A. Jitter (cycle-to-cycle) = T1 – T0
B. Jitter (peak-to-peak) = MAX{T0:Tn} – MIN{T0:Tn}
T0
T1
Tn
Figure 2. Jitter Measurement
P
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