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參數(shù)資料
| 型號(hào)： | CDC9441 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DVD System Clock Synthesizerers(PC時(shí)鐘合成器/驅(qū)動(dòng)器(SDRAM 時(shí)鐘支持)) |
| 中文描述： | DVD系統(tǒng)時(shí)鐘Synthesizerers（電腦時(shí)鐘合成器/驅(qū)動(dòng)器（SDRAM的時(shí)鐘支持）） |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大小： | 275K |
| 代理商： | CDC9441 |
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CDC9441
PC CLOCK SYNTHESIZER/DRIVER
WITH SDRAM CLOCK SUPPORT
SCAS578 – AUGUST 1996
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
Stabilization time
After PWRDN
↓
After power up
3
ms
3
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at XIN.
switching characteristics, CPU clocks (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
Period
CPUn
SEL = H
15
ns
SEL = L
16.7
Jitter
tr§
tf§
Duty cycle
tskew
CPUn
±
250
ps
CPUn
0.4
1.6
ns
CPUn
0.4
1.6
ns
CPUn
45
55
%
CPUn
CPUn
250
ps
Clock enable latency
CPUEN
CPUn
1
4
CPU
cycles
Specifications are applicable only after the PLL stabilization time has elapsed.
§Rise and fall times are characterized using the test circuit shown in Figure 1.
switching characteristics, SDRAM clocks (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
Period
SDRAMn
SEL = H
15
ns
SEL = L
16.7
Jitter
tr§
tf§
Duty cycle
tskew
Clock enable latency
Specifications are applicable only after the PLL stabilization time has elapsed.
§Rise and fall times are characterized using the test circuit shown in Figure 1.
SDRAMn
±
250
ps
SDRAMn
0.4
1.33
ns
SDRAMn
0.4
1.33
ns
SDRAMn
45
55
%
SDRAMn
SDRAMn
500
ps
CPUn
SDRAMn
500
ps
P
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| CDC950DGGRG4 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Fully Int Lo-Jitter Crstal Osc Clock Gen RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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