參數資料
型號: CDC9441
廠商: Texas Instruments, Inc.
英文描述: DVD System Clock Synthesizerers(PC時鐘合成器/驅動器(SDRAM 時鐘支持))
中文描述: DVD系統時鐘Synthesizerers(電腦時鐘合成器/驅動器(SDRAM的時鐘支持))
文件頁數: 2/14頁
文件大?。?/td> 275K
代理商: CDC9441
CDC9441
PC CLOCK SYNTHESIZER/DRIVER
WITH SDRAM CLOCK SUPPORT
SCAS578 – AUGUST 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
TYPE
FUNCTION
NAME
NO.
CPU(0:3)
41, 41, 43, 44
O
2.5-V CPU clock outputs with programmable frequency. These outputs can be
disabled to a logic low by deasserting CPUEN in the mobile mode (i.e., MODE = L).
IOAPIC(0:1)
46, 47
O
2.5 V, 14.318-MHz APIC clock outputs
MODE
25
I
Desktop or mobile mode select. When MODE = H, the device functions in the desktop
mode and pins 31, 29, and 28 are outputs SDRAM5, SDRAM6, and SDRAM7,
respectively. When MODE = L, the device functions in the mobile mode and pins 31,
29, and 28 are inputs PWRDN, CPUEN, and PCIEN, respectively. A 100-k
(nominal) pullup resistor is internally integrated so the default is the desktop mode.
PCI_F
7
O
3.3-V free-running PCI clock output at one-half the CPU clock frequency. PCI_F is
not disabled via the PCIEN signal.
PCI(0:5)
8, 10, 11, 12, 13, 15
O
3.3-V PCI clock outputs at one-half the CPU clock frequency. These outputs can be
disabled to a logic low by deasserting PCIEN in the mobile mode (i.e., MODE = L).
REF0
2
O
3.3 V, 14.318-MHz ISA reference clock output
SCLOCK
24
I
IIC serial clock input
SDATA
23
I/O
IIC serial data input/out
SDRAM(0:4)
SDRAM(8:11)
17, 18, 20, 21,
32, 34, 35, 37, 38
O
3.3-V SDRAM clock outputs synchronous and in-phase with the CPU clock outputs.
SDRAM5/PWRDN
31
I/O
3.3 V SDRAM clock output or power-down enable input based on the condition of the
MODE control input. When MODE = H, this pin functions as a 3.3 V SDRAM clock
output. When MODE = L, this pin functions as the PWRDN control input, which can
be used to disable all outputs to a low state and place the integrated oscillator and
PLL in a static state for low power consumption.
SDRAM6/CPUEN
28
I/O
3.3-V SDRAM clock output or CPU clock bank-enable input based on the condition
of the MODE control input. When MODE = H, this pin functions as a 3.3-V SDRAM
clock output. When MODE = L, this pin functions as the CPUEN control input, which
can be used to enable or disable the CPU clock outputs.
SDRAM7/PCIEN
27
I/O
3.3-V SDRAM clock output or PCI bank-enable input based on the condition of the
MODE control input. When MODE = H, this pin functions as a 3.3-V SDRAM clock
output. When MODE = L, this pin functions as the PCIEN control input, which can be
used to enable or disable the PCI clock outputs, with the exception of PCI_F.
SEL
26
I
Clock frequency select. When SEL = H, the CPU clock power-up frequency is
66.67 MHz. When SEL = L, the CPU clock power-up frequency is 60 MHz. A 100-k
(nominal) pullup resistor is internally integrated so the default power-up condition is
66.67 MHz.
XIN
4
I
Crystal input. The oscillator is designed for use with a 50-PPM, 18-pF parallel
resonant crystal. A TTL-level clock also can drive this input.
XOUT
5
O
Crystal output.
VCC
VCCO2
VCCO3
1
Power
3.3-V core power supply
42, 48
Power
2.5-V output power supply
6, 14, 19, 30, 36
Power
3.3-V output power supply
GND
3, 9, 16, 22, 27, 33,
39, 45
Ground
Ground
P
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