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參數(shù)資料
| 型號： | CDC922DLR |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 292K |
| 代理商： | CDC922DLR |
CDC922
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS634 –JULY 28, 1999
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics, V
DD
= 2.375 V to 2.625 V, T
A
= 0
°
C to 85
°
C (continued)
CPUx
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ten1
tdis1
Output enable time
SEL133/100
CPUx
f(CPU) = 100 or 133MHz
f(CPU) = 100 or 133MHz
f(CPU) = 100 MHz
f(CPU) = 133 MHz
f(CPU) = 100 or 133MHz
f(CPU) = 100 or 133MHz
f(CPU) = 100 or 133MHz
f(CPU) = 100 or 133MHz
6
10
ns
Output disable time
SEL133/100
CPUx
8
10
ns
tc
CPU clock period
10
10.04
10.2
ns
7.5
7.53
7.7
ns
Cycle to cycle jitter
250
ps
Duty cycle
45
55
%
tsk(o)
tsk(p)
t(off)
t(off)
CPU bus skew
CPUx
CPUx
50
175
ps
CPU pulse skew
CPUn
CPUn
2.2
ns
CPU clock to APIC clock offset, rising edge
1.5
2.8
4
ns
CPU clock to 3V66 clock offset, rising edge
0
0.75
1.5
ns
t1
tw1
Pulse duration width high
Pulse duration width, high
f(CPU) = 100 MHz
f(CPU) = 133 MHz
f(CPU) = 100 MHz
f(CPU) = 133 MHz
VO = 0.4 V to 2.0 V
VO = 0.4 V to 2.0 V
2.6
4.3
ns
1.4
3.7
t2
tw2
Pulse duration width low
Pulse duration width, low
2.8
4.3
ns
1.7
4
tr
tf
Rise time
0.4
1.5
2.2
ns
Fall time
0.4
1.4
2
ns
The average over any 1-
μ
s period of time is greater than the minimum specified period.
CPU_DIV2
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ten1
tdis1
Output enable time
SEL133/100
CPU_DIV2
f(CPU) = 100 or 133MHz
f(CPU) = 100 or 133MHz
f(CPU) = 100 MHz
f(CPU) = 133 MHz
f(CPU) = 100 or 133MHz
f(CPU) = 100 or 133MHz
f(CPU) = 100 or 133MHz
f(CPU) = 100 MHz
f(CPU) = 133 MHz
f(CPU) = 100 MHz
f(CPU) = 133 MHz
VO = 0.4 V to 2.0 V
VO = 0.4 V to 2.0 V
6
10
ns
Output disable time
SEL133/100
CPU_DIV2
8
10
ns
tc
CPU DIV2 clock period
CPU_DIV2 clock period
20
20.08
20.4
ns
15
15.06
15.3
ns
Cycle to cycle jitter
250
ps
Duty cycle
45
55
%
tsk(p)
CPU_DIV2 pulse skew
1.6
ns
t1
tw1
Pulse duration width high
Pulse duration width, high
7.1
ns
4.7
t2
tw2
Pulse duration width low
Pulse duration width, low
7.3
8.9
ns
5
6.6
tr
tf
Rise time
0.4
1.4
2
ns
Fall time
0.4
1.3
1.8
ns
The average over any 1-
μ
s period of time is greater than the minimum specified period.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CDC924 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIRECT RAMBUSE CLOCK GENERATOR |
| CDC924DL | 功能描述:時鐘合成器/抖動清除器 133MHz Clk Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDC924DLG4 | 功能描述:時鐘合成器/抖動清除器 133MHz Clk Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDC924DLR | 功能描述:時鐘合成器/抖動清除器 PC Motherboard 133- MHz Clock Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDC924DLRG4 | 功能描述:時鐘合成器/抖動清除器 PC Motherboard 133- MHz Clock Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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