參數(shù)資料
型號: CDC339DWR
廠商: Texas Instruments, Inc.
英文描述: Eight Distributed-Output Clock Driver
中文描述: 八分布式輸出時鐘驅動器
文件頁數(shù): 5/7頁
文件大?。?/td> 105K
代理商: CDC339DWR
CDC339
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS331 – DECEMBER 1992 – REVISED MARCH 1994
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7 V
Open
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note C)
Output
Waveform 2
S1 at Open
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
3 V
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
tPLH
tPHL
Output
1.5 V
1.5 V
3 V
0 V
1.5 V
VOH
VOL
Input
0.8 V
2 V
tr
0.8 V
2 V
tf
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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