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參數(shù)資料
| 型號： | CDC3244 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V ABT Octal Clock Driver with 3 State Output(3.3VABT八時鐘驅動器(三態(tài)輸出)) |
| 中文描述： | 3.3 - 3國輸出V ABT生根粉八路時鐘驅動器（3.3VABT八時鐘驅動器（三態(tài)輸出）） |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 148K |
| 代理商： | CDC3244 |
CDC3244
3.3-V ABT OCTAL CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS500 – APRIL 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CLOCK DRIVER CIRCUITS
1.5 V
th
tsu
From Output
Under Test
CL = 15 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
6 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
2.7 V
0 V
1.5 V
1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
, tr
≤
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
P
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