參數(shù)資料
型號: CDC2516DGG
廠商: Texas Instruments, Inc.
英文描述: 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
中文描述: 3.3 - V相位鎖相環(huán)時鐘驅動器
文件頁數(shù): 9/11頁
文件大?。?/td> 160K
代理商: CDC2516DGG
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 3
PHASE ERROR
vs
CLOCK FREQUENCY
–400
–600
–800
–1000
55
95
fclk – Clock Frequency – MHz
–300
–500
–700
–900
75
115
135
VDD = 3.3 V
TA = 25
°
C
–200
0
35
P
–100
Figure 4
VDD = 3.3 V
CL = 30 pF
OUTPUT DUTY CYCLE
vs
CLOCK FREQUENCY
57%
53%
51%
47%
43%
55%
49%
45%
O
50
70
110
fclk – Clock Frequency – MHz
90
130
30
Figure 5
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
25
6
4
2
0
35
45
55
85
95
fclk – Clock Frequency – MHz
75
7
A
5
3
1
65
105 115 125
8
9
VDD = 3.3 V
TA = 25
°
C
Figure 6
DYNAMIC SUPPLY CURRENT
vs
CLOCK FREQUENCY
300
200
100
0
fclk – Clock Frequency – MHz
350
D
250
150
50
400
450
500
0
20
40
60
120
140
100
80
VCC = 3.6 V
Bias = 0/3 V
CL = 30 pF to GND
TA = 25
°
C
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