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參數(shù)資料
| 型號(hào)： | CDC2516DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 3.3 - V相位鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | CDC2516DGG |
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
CLK
12
I
Clock input. CLK provides the clock signal to be distributed by the CDC2516 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
FBIN
37
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
1G
9
I
Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same
frequency as CLK.
2G
16
I
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
3G
33
I
Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are
disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same
frequency as CLK.
4G
40
I
Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are
disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same
frequency as CLK.
FBOUT
35
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-
series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G.
These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output
has an integrated 25-
series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G.
These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output
has an integrated 25-
series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G.
These outputs can be disabled to a logic-low state by deasserting the 3G control input. Each output
has an integrated 25-
series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G.
These outputs can be disabled to a logic-low state by deasserting the 4G control input. Each output
has an integrated 25-
series-damping resistor.
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is
bypassed and CLK is buffered directly to the device outputs.
1Y(0:3)
2, 3, 6, 7
O
2Y(0:3)
18, 19, 22, 26
O
3Y(0:3)
31, 30, 27, 26
O
4Y(0:3)
47, 46, 43, 42
O
AVCC
11, 38
Power
AGND
13, 14, 36
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
1, 8, 17, 24,
25, 32, 41, 48
Power
Power supply
GND
4, 5, 10, 15,
20, 21, 28, 29,
34, 39, 44, 45
Ground
Ground
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| CDC2516DGGR | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3VPhase Lock Loop ClockDrvr RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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| CDC2536 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS |
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