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參數(shù)資料
| 型號(hào)： | CDB5532U |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5532U ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 35mW @ 3.84kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5532 |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | CS5532-BSZR-ND - IC ADC 24BIT 2CH W/LNA 20-SSOP CS5532-ASZR-ND - IC ADC 24BIT 2CH W/LNA 20-SSOP 598-1113-5-ND - IC ADC 24BIT 2CH W/LNA 20SSOP 598-1112-5-ND - IC ADC 24BIT 2CH W/LNA 20SSOP |
| 其它名稱： | 598-1159 |
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IDT / ICS PCI EXPRESS JITTER ATTENUATOR
8
ICS9DB202CK-01 REV. B FEBRUARY 18, 2009
ICS9DB202-01
PCI EXPRESS JITTER ATTENUATOR
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electr ical perfor mance, a land patter n must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in
Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the
Surface Mount Assembly of Amkor’s Thermally/
Electr ically Enhance Leadframe Base Package, Amkor
Technology.
THERMAL VIA
LAND PATTERN
SOLDER
PIN
SOLDER
PIN PAD
PIN
GROUND PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB5534U | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 Eval Bd 24Bit ADC w/ Ultra Low-Noise USB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| CDB5534U-Z | 功能描述:EVAL BD 24-BIT ADCS W/ULTRALN PG 制造商:cirrus logic inc. 系列:- 零件狀態(tài):在售 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):24 采樣率（每秒）:3.84k 數(shù)據(jù)接口:串行 輸入范圍:±2.5 V 不同條件下的功率（典型值）:35mW @ 3.84kSPS 使用的 IC/零件:CS5534 所含物品:板，電纜 標(biāo)準(zhǔn)包裝:1 |
| CDB5540 | 制造商:Cirrus Logic 功能描述:EVAL BOARD FOR CS5540 - Bulk |
| CDB5541 | 制造商:Cirrus Logic 功能描述:EVAL BOARD FOR 5540 & 5541 N/A - Bulk 制造商:Cirrus Logic 功能描述:Tools Development kit For Use |
| CDB5550 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Evaluation Board and Software |
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