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參數(shù)資料
| 型號(hào)： | CDB5532U |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS5532U ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 35mW @ 3.84kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5532 |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | CS5532-BSZR-ND - IC ADC 24BIT 2CH W/LNA 20-SSOP CS5532-ASZR-ND - IC ADC 24BIT 2CH W/LNA 20-SSOP 598-1113-5-ND - IC ADC 24BIT 2CH W/LNA 20SSOP 598-1112-5-ND - IC ADC 24BIT 2CH W/LNA 20SSOP |
| 其它名稱： | 598-1159 |
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
7
ICS9DB202CK-01 REV. B FEBRUARY 18, 2009
ICS9DB202-01
PCI EXPRESS JITTER ATTENUATOR
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
PP
and V
CMR input
requirements. Figures
4A to 4F show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
HIPERCLOCKS LVHSTL DRIVER
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
HCSL
*R3
33
*R4
33
CLK
nCLK
2.5V
3.3V
Zo = 50
Ω
Zo = 50
Ω
HiPerClockS
Input
R1
50
R2
50
*Optional – R3 and R4 can be 0
Ω
FIGURE 3F.
HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
CLK
nCLK
HiPerClockS
SSTL
2.5V
Zo = 60
Ω
Zo = 60
Ω
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
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